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DVCon "Day 0" - Quick Report From SystemC Day

Comments(1)Filed under: Functional Verification, System Verification, SystemC, DVcon, ESL, TLM

If you were looking for more evidence that the transition from RTL to ESL is gaining momentum, today at "Day 0" of DVCon (a/k/a "SystemC Day") you would discover plenty of supporting data points.  Here is a brief video interview with my colleague Steve Svoboda on the day's events, how far we've come from the first wave of SystemC hype back in 2000, and what Cadence is doing in this space:


If the video fails to launch click here.

Additionally, I had the pleasure of sitting in on the TLM 2.0 tutorial.  While all 3 presenters -- John Aynsley of Doulos, Michael "Mac" McNamara of Cadence, and Michael Meredith of Forte -- had a great mix of detailed technical & high-level information.  In particular, Mac's blunt declaration, "You can keep your head in the sand, or realize that today we need to move to higher abstraction for design and verification", was a bracing standout.


Mac outlines to the TLM 2.0 tutorial audience why the time for higher level abstraction is NOW.

Bottom-line: this "day 0" of events was a great warm-up for the rest of the show, and I'm looking forward to day 1!

Joe Hupcey III

Reference Links
The official DVCon site

Comprehensive list of Cadence-sponsored events & papers
(Be sure to sign up for our free lunch panel on the growing debug crisis on Wednesday)

Images from last year's show to give you an idea of what it's like, in case you have never been to a DVCon before.



By Michal on February 24, 2010
Very insightful - great to see the industry momentum around raising the design and verification abstraction from RTL to TLM!

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