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DVCon 2010 For The Specmaniac

Comments(0)Filed under: Functional Verification, OVM, eRM, SystemVerilog, SystemC, e, Specman, OVM e, OOP, AOP, Object Oriented Programming, DVcon, IES-XL, Mike Stellfox, Incisive, AMIQ, MDV, OVM ML, TLM

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored activities is posted here).  Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs.  Hence, if you are going to the event, please consider printing out the following "DVCon 2010 Guide for the Specmaniac".

Monday February 22 - "SystemC & ESL day"

Granted, day 1 of the program is not really called "SystemC & ESL day"; and it's not even about Specman or the e language.  However, it's clear that the trend of DUTs moving from RTL languages to higher abstraction with SystemC is starting to snowball (as at least 15-20% of Specmaniacs already know).  Hence, depending on the degree to which your projects are aligned with this trend, Specmaniacs should attend either the North American SystemC Users' Group meeting on Monday morning, or the TLM 2.0 tutorial in the afternoon, or both.  (Related FAQ: if ESL / TLM / SystemC is the wave of the future for design, is it the wave of the future for verification too?  The paper being given by Cadence R&D Architect Matan Vax on Thursday morning (highlighted below) will address this question head on ...)

Tuesday February 23, 1:30pm-5:00pm, (Fir Ballroom):

Tutorial on OVM Advanced Applications

This techtorial will include updates on OVM e itself, as well as in the context of advanced applications like multi-language testbench integration, Verification IP (VIP) creation & integration, low power, and acceleration.  Come prepared to take plenty of notes because the presenters will walk through many detailed code examples.

Tuesday Feb. 23 and Wednesday Feb 24, 2:00pm-6:30pm:

Specman technology in the Cadence booth (#505)
As always, Specman technology is directly or indirectly a cornerstone of the various demos -- OVM, Verification IP, metric-driven verification & Enterprise Manager updates, ESL & TLM updates, etc.  The best part: at a relatively small show like DVCon, there is often the opportunity to digress from the primary demos and deep dive into specific Specman technology updates -- just ask us!

Additionally: our partner AMIQ has a booth at DVCon, where they will be showing new features in their DVT integrated development environment.  To whet your appetite, here is a brief demo of rapid e coding with DVT, and some general background on the company itself.

Wednesday February 24, Session 4, Paper 4.2 at 11am, Oak room

Paper: "Apples Versus Apples HVL Comparison Finally Arrives"

Ever wondered how languages like e, SystemVerilog, and SystemC stack up for different applications and use cases in a straightforward, side-by-side comparison?  If so, this is the paper you have been waiting for!

Wednesday February 24, Lunch Panel 12:30-1:45pm, Pine/Cedar room

OVM Found the Bugs, Now How Do We Debug Them Faster?
Clearly, streamlining the debug progress is of high importance to Specmaniacs, so please join us for this important panel discussion. 

Note: the M.C. for the panel will be familiar to many Specmaniacs: Distinguished Engineer Mike Stellfox.  Be sure to re-connect with Mike before or after the panel; or even better, during the panel fire off a question to him and/or one to vector to the panelists.

Wednesday February 24, 2:00 - 3:00pm, Oak/Fir room

Keynote Presentation: Breaking Through the Efficiency Barrier

As with the lunch panel, while this keynote by our CEO Lip-Bu Tan isn't directly about Specman (IMHO, a missed opportunity, but he *is* the boss ;-)  the speech's focus on how companies can break through the efficiency barrier with higher abstractions of design and verification, reuse, metrics, and up-front tradeoffs is of obvious importance to anyone in D&V.

Thursday February 25, Session 7, Paper 7.1 at 8:30am, Siskiyou room

Paper: "Where OOP Falls Short of Verification Needs"
Presented by Cadence R&D Architect Matan Vax, the paper title says it all: at a certain point on the scalability curve, OOP-based languages start to break, given the unique requirements of verification itself -- vs. design-oriented applications like ESL or firmware development.  To put a finer point on it: this paper will enable Specmaniacs to describe exactly why e is perfectly suited for massively scalable verification environments. 

FYI, if you are into the nuances of languages in general, be sure to chat with Matan since he is a walking Rosetta Stone of D&V languages.

Thursday February 25, Session 7, Paper 9.3 at 10:30am, Cascade room

Paper: "Tweak-Free Reuse Using OVM"
While bits of this paper will be old news for long time eRM, er, OVM e users, Solutions Architect Sharon Rosenberg (another familiar face to many Specmaniacs!) will cover a lot of new ground and emerging best practices he is seeing at the many customers he's called on in the past year.

Last but not least:
It bears repeating that verification gurus like R&D Architect Matan Vax, Distinguished Engineer Mike Stellfox, Solutions Architect Sharon Rosenberg, and many others will be at DVCon to hear your latest verification-specific concerns and challenges.  If you don't run in to them in the conference halls, just ask any Cadence person help locate them.

We look forward to seeing you next week!

Team Specman

Reference links
The official DVCon site

Comprehensive list of Cadence-sponsored events & papers

Images from last year's show to give you an idea of what it's like, in case you have never been to a DVCon before.



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