Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models encounter unknowns propagated from shutdown blocks?
For the unprepared, the simulation fails. In most cases. the models were written before low-power simulations were conceived. They do not take into account the fact that their inputs can go to X at any time during the simulation run (as opposed to just a short while after time 0). We have seen many C-models crash when one or more of the inputs goes to X (this simulates the driving block being shut-down). If you have this configuration in your chip, you must isolate all inputs going to the C-model before shutting down any driving blocks that are connected to the model’s inputs.
Another thing to avoid is shutting down the C-model. You must put it in an always-on domain. The Incisive simulator (IES-XL) often does not have access to the internals of the model so it cannot properly handle the low-power operations that are necessary to power down the model. All power-down functions must be done natively in the model if you need it to work properly in shut-down.
A third thing to look for is any driving or receiving net that is connected to the model. Proper drive/load analysis cannot be done when originating or terminating in the model. For instance, for all model inputs, the CPF command to specify isolation must be of the form:
create_isolation_rule -name xxx -from <driving_power_domain>...
When written in this form, only the driver must be located, not the receiver, so isolation will be placed properly.
Likewise, for all model outputs that need to be isolated, use the following form:
create_isolation_rule -name xxx -to <receiving_power_domain>...
This will remove the need to find drivers inside of the model.
Finally, we are introducing a new capability that will allow users to have a SystemC module in their Verilog or VHDL testbench and still use the automatically generated low-power assertions. If you have a need for this capability, contact us at genIES@cadence.com today for an early look.