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A Look Back On 2009 (Before Hazarding Predictions For 2010)

Comments(0)Filed under: Functional Verification, SystemVerilog, metric driven verification (MDV), coverage driven verification (CDV), multi-language, SystemC, e, C, EDA, MDV, ESL

Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against the main verification technology-specific observations that I saw throughout the year.

Prediction 1: all of the following would become more intense:

  1. 1 billion logic gate chip roadmaps are here
  2. True "Metric Driven Verification" (MDV) starts to evolve from CDV
  3. The "language war" is over -- all languages won!
  4. Pre-silicon HW/SW co-verification became too important to ignore
  5. Analog+Digital verification frustration grows
  6. Low Power pain continues

2009 history:
Looking at the list above, I have to say each trend largely continued to build in 2009 as predicted, with the exceptions items #2 of #3. Specifically:

Regarding MDV growth:
From what I could tell from my travels and field reports, it seems that metric driven verification — the tracking & recording metrics beyond the basics of code & functional coverage — gained more traction in 2009 outside the vanguard of customers who initially adopted the methodology.  [Cadence self-promo alert]  Furthermore, with the addition of metric export capabilities to Incisive Formal Verifyer, not to mention the embedding such capabilities inside the new Incisive Enterprise Verifier formal+simulation tool, the historically isolated formal verification flow is now literally more visible in the verification process.

Regarding languages:
The advent of ESL (discussed next) is stirring the language pot all over again in some quarters, where the question arises whether the C / C++ / SystemC used for architectural exploration and design activity should also be extended for ESL verification.  Long story short (and what could be the subject of several blog posts), and I see the smart money concluding they must "use the right tool for the right job", meaning e and SystemVerilog remain the best choices for verification, and SystemC keeps its crown as the king of architectural exploration and ESL-level design capture.

Prediction 2: ESL *almost* goes mainstream

2009 history:
As cited in a prior post on "Observations From This Autumn's Events", I think that ESL's time has finally come.  To an extent that surprised me, it was evident that more customers were asking about ESL-related solutions for real projects vs. CAD department experiments.  I dare say that after an Indiana Jones like leap across the chasm, ESL is starting to climb the growth curve.  If you are a specialist in RTL tools & methodologies, and this news surprises you, I strongly recommend you start following my colleagues' System Design and Verification blog stream (and read and internalize all the prior posts too).

Prediction 3: IP management will become critically important

2009 history:
This is one prediction that is simultaneously hard and easy to prove whether it's come true or not.  With few exceptions, the difficulty lies in the fact that customers rarely report this pain to us [the EDA community] directly.  Instead, a lot of the blame for problems in this area are assigned to IT systems and/or non-EDA tools that are being bent into shape to support a mélange of RTL design, ESL design, verification components, analog models, etc.  Instead of asking us about this, I'm sure many customers are complaining to Oracle, MySQL (maybe for not much longer), Microsoft, or whoever their database provider of choice may be.

That said, reality of this situation is relatively easy to confirm when you take a second to actually look at what customers trying to feed into the EDA tool chain IP managed by this essentially ad hoc process.  Even worse, all this is going on despite the best efforts of people working on interoperability/API/data sharing initiatives like IP-XACT.

I'm eager to hear your reaction to these observations, so feel free to post some comments below or contact me offline.

Finally: Happy New Year!

Joe Hupcey III

P.S. As you may have noticed, the frequency of posts to this blog have dramatically decreased since I signed onto Twitter (Follow me!  http://twitter.com/jhupcey).  The relationship is causal: to my pleasant surprise I've found Twitter's microblogging much easier to squeeze into the nooks and crannies of my schedule.  That said, there is only so much information you can squeeze into a series of 140 character chunks, let alone the limited nature of the Twitter-related photo and video sharing options.  Thus (especially with major events like DVCon right around the corner) I look forward to writing more long form articles on this blog stream, albeit at a lower frequency.



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