Home > Community > Blogs > Functional Verification > scalability made ovm the ideal choice for uvm
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Scalability Made OVM The Ideal Choice For UVM

Comments(0)Filed under: Functional Verification, Simulation acceleration, OVM, SystemVerilog, e, performance, MDV, OVM ML, uvm

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted in it's uniquely scalable architecture.  Today's announcement by Mitsubishi Electric and the OVM Advanced Topics tutorial at DVCon are examples of scalability beyond the common SystemVerilog testbench.

For some verification teams, jumping head-first into the maw of object-oriented programming is daunting.  Object-oriented programming does require a series of fundamental shifts in thinking including writing code for objects that will come in and out of existance during simulation, the ability to override types to localize VIP rather than rewriting it, constrained-random inputs, and more.  For engineers that have built directed testbenches for years, aquiring all of this knowledge and applying it while maintaining schedule and quality commitments is a daunting task.  Mitsubishi found that the module-based overlay provided by Cadence enables the full OVM methodology while creating a static strucure that makes implementing the first object-oriented testbench easier.

At the other end of the scalability spectrum are the OVM Advanced Topics.  Among these are multi-langauge support for e and SystemC, low-power verification using OVM sequences to set-up power-states in the DUT, acceleration for verification performance, and ABV to both utilize assertions with OVM and to include formal analysis in an overall metric driven verification methodology that includes formal. At DVCon on Tuesday February 23rd Cadence verification experts will lead an interactive tutorial on these advanced topics so be sure to register early!

So with the UVM coming soon, how will OVM and future UVM users access all of this advanced technology? First, all of the advanced topics work with the existing OVM 2.1 release so we expect that they will work with UVM 1.0 as it will be based on OVM.  Second and more importantly, many of these are available to users right now in the OVM World contributions area.  If any of these are interesting to you and you want them to be included in the UVM 1.x releases, please contact your Accellera rep or join the VIP TSC and make your wishes known!

Are you using OVM for advanced verification?  Our blog readers are always ready for a good technical story!

=Adam Sheriblog

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.