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Formalizing Multilanguage Mixology For e Users

Comments(0)Filed under: Functional Verification, OVM, SystemVerilog, multi-language, SystemC, VIP, Cadence VIP portfolio, e, Specman, OVM e, C, IES-XL, sequences, ESL, TLM, Matlab, methodology

Historically it’s been very common for e users to have to mix other programming languages with their e verification environment.  Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non-e testbenches, or even interfacing to Matlab models.  To stay in the vanguard of this ongoing trend, the 9.2 Update release posted last week is specifically aimed at formalizing additional multi-language support for verification in general, including e/Specman-specific enhancements. So what is important to you as an e user?  First, consider the following three most common use cases:

e “over” SystemVerilog
This is the case where you want to take advantage of some SystemVerilog Verification IP (VIP) in your e based environment.  A new SoC Kit workshop guides you through how to use new 9.2 Update technology features like OVM method ports, new utilities like mltypemap (described below), and multi-language sequences to incorporate / reuse that SystemVerilog VIP in your e testbench.

SystemVerilog “over” e
In this case, you want to deliver some e VIP to your SystemVerilog colleagues that don’t wish to know anything about the e language (their loss, eh?)  To support this, enhancements to the OVM Interface Generator (OIG), along with the SOC kit introduction of the GUI based OVM Interface Configurator (OIC), provide the means necessary to create an SystemVerilog API to your e VIP.  Again, the workshop in the SoC Kit guides you through the steps to use these utilities.

Integrating SystemC reference models into your e environment
Clearly the main technology enabler here is TLM ports.  As noted in some earlier Team Specman posts, the team has been steadily enhancing the e implementation of TLM ports that will help in creating multi language environments, and as will be discussed in more detail below, the 9.2 Update release is another step in this direction.

Keeping the above use cases in mind, let’s turn around to another perspective, and review the highlights about the specific multi-language related technologies introduced in the 9.2 Update release.

OVM Interface Generator (OIG) and OVM Interface Configurator (OIC) – These utilities are used to create a SystemVerilog interface for an existing e VIP.  The new OIC utility, which is shipped as part of SoC Kit, provides a handy GUI front end to OIG that reads in the e VIP and then guides the user through a series of questions to create both the OIG input files as well as an example environment demonstrating the SystemVerilog interface.  In the 9.2 Update release the way that e sequences are exported was improved to make the connection between SystemVerilog sequences and e sequences more direct.  This improvement enables layering sequence drivers, and removes many limitations such as grab/ungrab across the language boundary.  (True story: these tools are used by Cadence’s own Verification IP R&D to rapidly develop VIP interfaces as required by the over 30 different protocols they are supporting.)

TLM ports – As hinted at above, TLM ports form the communication backbone between all three languages in OVM.  The 9.2 update release brings some improvement to their support in e.

  1. Support for hierarchical binding. (i.e. using exports to make TLM port connections)  Now an external interface can be presented at a higher level unit such as an environment or an agent, while the actual port lives in a lower layer component like a BFM or monitor.
  2. Support for multiple binding of e analysis ports. In the 9.2 update release e TLM analysis ports can be connected to multiple sources or destinations, including connections across a language boundary.

OVM Method ports – These ports have been in the tools as an “early adopter" feature for a couple releases, and thanks to feedback from curious Specmaniacs they have now achieved production status.  In a nutshell, the way they work is that these new ports give a method port-like interface in both directions between e and SystemVerilog. As such, they provide a more flexible interface between e and SystemVerilog than TLM ports, but they are completely complimentary.

Mltypemap – This is a new utility built into %irun that allows the user to map types from one language to another.  For example, have you ever wondered what your e struct would look like in SystemVerilog or SystemC?  Using this utility you can now quickly find out. The utility is featured as part of the e over SystemVerilog workshop where it is used to map SystemVerilog types into e constructs.  Note that in the 9.2 update this feature is still early adopter, but I still suggest giving it a try and sharing your feedback with the community.

Multilanguage SOC kit workshops – There have been some great updates to the SoC Kit workshop collection in the area of Multi Language.  There is a new workshop that illustrates the e over SystemVerilog use case that walks the user through the steps needed to reuse an SystemVerilog VIP in an e environment.  There were also improvements made to the existing SystemVerilog over e workshop including the steps needed to migrate a previous OIG export to the new Multi Language sequence model.


Finally, since this will be our last post for 2009, on behalf of Team Specman allow me to thank you for tuning into our posts this past year.  Have a great holiday season!!!

Brett Lammers
CoreComp Sr. Technical Leader

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