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Verification is a Sprint and a Marathon!

Comments(0)Filed under: Functional Verification, Simulation acceleration, OVM, SystemVerilog, IES, performance, Incisive, Low-power, multi-core

Verification engineers have updated an old adage to discribe their projects:  Verification is both a sprint and a marathon!  We need to optimize everything from single simulation runs to the complete suite of regression tests and every task in between.  Cadence answered that comprehensive call in the Performance Leadership announcement issued September 29th, 2009.

This intrepid blogger thrives in the land of performance and productivity.  It pervades all aspects of Incisive.  While the announcement cited the Incisive Enterprise Simulator family and the Incisive Palladium series, the actual performance capabilities go much deeper.  We are tuning performance in all areas including gate/RTL, ESL, coverage, generation, hardware, low-power, and more.  While multi-core is the news in this announcement, we have more tricks up our sleeves. In fact, you can see from the picture below, this blogger even carries the Incisive performance message to the streets of Boston. (That's 3 hrs of free advertising to 500,000 people!)


You can also learn more about our performance capabilities at CDNLive! in the webinar entitled "Verification Performance: Where is my Go Faster Button?"  This webinar will be accompanied by a performance handbook to help you tune your verification environments at all levels.

So as I put my application in for my 9th consecutive Boston Marathon, I'm asking myself "how can I go faster?"  How will you go faster in your projects?

=Adam Sherilog



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