Home > Community > Blogs > Functional Verification > Simulation of Voltage Scaling for Dynamic Power Reduction
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Simulation of Voltage Scaling for Dynamic Power Reduction

Comments(1)Filed under: Functional Verification, Low Power, signal integrity, verification, Real Value Modeling, wreals, advanced node, Mixed-Signal

Some background info:
In a previous blog, I introduced:

  • DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction.
  • RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings. See “Part1: Using wreals to simulate Frequency Scaling for Dynamic Power Reduction” for details

In that blog, I addressed Frequency Scaling using wreals modeling. Now, allow me to focus on how to simulate Voltage Scaling also using RVM. The full topic will be covered in a series of blogs. This is a first one of a series…

Controlled Voltage source:
Here’s an example of using advanced techniques in the testbench to create a controlled voltage source - in this case using constrained random generation of real numbers in Specman. A noisy voltage-source, such as a battery supply that varies over time and also drifts with temperature and use can be created as shown in this blog. The battery-voltage is supplied to an LDO that serves to regulate the noisy voltage so that it can be used for precise voltage variations used in voltage scaling of design elements.




But first, let’s look at the voltage generation the TB. Example below shows how Specman gets access to the DUT and other HDL elements in the Verification Env using hdl_paths() and port-maps. There ere two possible scenarios:

  1. Use externally supplied constraints for min/max voltage values
  2. Specify min/max voltage constraints form within the Specman env.

In either case, voltage values are created within the supplied constraints using a rdist_uniform() routine to generate real numbers.

rdist_uniform(from : real, to :real): real
Returns a random real number using uniform distribution in the range from to to.

This feature does require the use of Intelligen solver which is invoked by a switch in irun: -snset "config gen -default_generator=IntelliGen"




The following constraints were used in this example, resulting in the voltage source – see waveform. The rate of voltage generation (samples per sec) can also be configured from the verification env.





In this blog, I covered how Voltages sources can be generated from the verification env. In the next blog I will cover how voltages get regulated with precision and then supplied to the various voltage islands on the chip. In the continuing series of blogs, I will then cover how nominal voltages are specified and controlled and how voltage scaling occurs with and modulated in a closed-loop env with feedback form individual design entities against targeted performance. I will also cover checking and coverage and error detection, including the effects of voltage overshoot/undershoot on system

Stay tuned for more…
Neyaz Khan


By Julian on October 7, 2009
There is a something that I don't understood how I should do.
In the timing simulation of digital modules if I change the voltage of a domain, I must change the .sdf file dynamically, since the propagation delay of my cells will change with.
Is the Incisive tool able to do this?

Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.