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Write Right OVM Verification Components

Comments(0)Filed under: OVMWorld, SystemVerilog, OVM e, OVM SV, OVM ML

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes. While its unique built-in classes are the technical heart of the reuse, you still have to write your own components. Now you have the new Paradigm Works OVC Template Generator to write them in the right way for you.

Paradigm Works, an industry leader in functional verification services has helped clients verify complex chips OVM SV and OVM e (eRM). The OVM Template Generator leverages Paradigm Works’ best-learned practices and offers pre-packaged verification environment templates that can be customized to further fit a team’s specific project requirements. The output of the Template Generator is an OVM compliant Verification Component (OVC).

To help us understand what the generator does and how it helps speed the verification process, I sat down with Dr. Ambar Sarkar. Dr. Sarkar is the Chief Verification Technologist at Paradigm Works Inc. and a self-declared open source enthusiast. He is the architect of the SystemVerilog FrameWorksTM toolkit, which includes the Template Generator, among other tools and utilities to jumpstart a verification environment. This toolkit is based on soup-to-nuts experience of the PW team at numerous client engagements.

Q: Ambar, can you tell us more about the Template Generator?

Simply put, the SystemVerilog FrameWorksTM Template Generator (SVF-TG) generates a detailed boilerplate for an OVM based verification environment (testbench) from scratch. The verification engineer is presented with a web interface where he or she enters a few parameters, and the resulting output is a tarball of the SystemVerilog environment code, with all the recommended components hooked up as recommended by OVM. From that point, the engineer needs to code the application-specific elements, but the plumbing that enables reuse has been taken care of already.

Q: Where can we find the Template Generator?

The Template generator is posted to the Contributions area of the OVM World.  This takes you to the web interface. We are working on putting the entire source code of the template generator on SourceForge, the popular open source software hosting site.

Q: How do we know that the templates are OVM compliant?

We held several detailed internal reviews with our core team of highly experienced verification engineers who bring their own perspective and their knowledge of the various application domains they have consulted for. In addition, we cross-checked the generated code against Cadence’s OVM compliance list. That list comprehends the nearly decade-long experience with OVM e (eRM) and the more recent experience with OVM SystemVerilog.

Q: Why not just code OVCs by hand following examples?

To summarize, I see two main reasons for not doing this by hand.

First, which is I believe is the main reason, is that this tool offers a standard and powerful starting point for the engineer embarking on a new OVM project. All the necessary element templates, specified by the engineer, have been defined and hooked up. In fact, even the makefiles for multiple simulator vendors are provided so that the generated code compiles out of the box.

Second, it avoids tedium. Frankly, there is a significant amount of infrastructure code that needs to be written and hooked up for any real project. Copying and pasting from an existing example has the usual caveats – what if you did not update everything you needed to or forgot to define some key elements? To illustrate this point, take a look at some code snippet that is generated. This was done for a simple scenario where the testbench needs 3 APB masters and 1 APB slave. As you can see, it is quite possible that one may forget to hook up or mistype one of the numbers or names.


function void connect();

[ deleted… ]

// Assign reference for virtual sequencer

v_sequencer.apb_0_m_sequencer = apb_inst.masters[0].sequencer;
v_sequencer.apb_1_m_sequencer = apb_inst.masters[1].sequencer;
v_sequencer.apb_2_m_sequencer = apb_inst.masters[2].sequencer;

v_sequencer.apb_0_s_sequencer = apb_inst.slaves[0].sequencer;

[deleted …]

endfunction : connect


Q: What kind of demand are you seeing for this functionality?

We have been very excited with the response so far. From the OVM community page, we see that there have already been more than 400 downloads in a relatively short time. That’s 340+ on OVM World and another 70+ directly from our PW page (http://downloads.paradigm-works.com).

Q: What else are you seeing the OVM ecosystem demand?

As far as the templates are concerned, we definitely had requests for customizing the generated code. The web interface does not allow it, but the backend tool supports complete customization, and even knows how to merge changes from newer templates. As I mentioned earlier, we are working on putting the entire backend on open source for the OVM community. Imagine the ability to come up with a standard way to create testbenches across all projects in a company distributed across the globe! This tool can act as an executable specification for creating testbenches.

We also have uploaded an objection based shutdown manager as well as an OVM scoreboard package. While there are some alternatives to the shutdown manager available, this powerful scoreboard package fills a void in the OVM community today.

Another area we are looking at, depending on bandwidth and community interest, is OVM multi-language, including e and SystemC. We would like to hear from the OVM community if there is an interest for creating templates for these OVM versions.

We encourage folks to visit http://downloads.paradigm-works.com, and stay tuned for further contributions on http://ovmworld.org/contributions.php. Of course, we look forward to and will incorporate any feedback as appropriate and feasible.

Do you have any questions for Ambar or me? If so, you can comment here on this blog or contact Ambar directly at ambar.sarkar@paradigm-works.com.

=Adam Sherilog


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