[Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch]
As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined. Even worse: there is no standard that specifies the order of execution of always blocks and VHDL processes, which can lead to simulation results in differing from an equivalent pure VHDL or pure Verilog simulation. Specifically, there are two very common problem scenarios, both of which can get trickier when Specman comes into the picture. Consider:
Scenario 1 - VHDL entities that drive Verilog regs and nets
In this scenario, Specman might sample Verilog signal values that are premature
Scenario 2 - Verilog entities drives VHDL signals
In this case, Specman might not sense a change on VHDL signals.
In order to better understand why these scenarios happen, let's look at a "normal" Specman-simulation cycle:
- First all signal updates are performed.
- Next, VHDL “processes” and Verilog “always” blocks are executed
- If executing these “process” and “always” blocks trigger more signal updates, then it loops, until all signal updates and process are executed. (You often hear this referred to as “the active region”.)
- Specman then synchronizes (i.e. samples values) just after that, and before the execution of non-blocking assignments (“NBAs”) list.
- Once all this is evaluated (the active region+Specman), then Verilog NBAs are executed.
- Since the VHDL language signal assignment statement always performs the signal value update in the next delta cycle (there is no blocking/non-blocking or any similar concept in VHDL), then at a given simulation time, for mixed language designs, Specman synchronizes after all VHDL signal updates have been done.
The following Diagram better illustrate this flow (Specman is operating in the "Red Zone"):
When you tie this sequence of activity to Scenario 1 above, Specman will sample the Verilog signal after it is already changed to the next value (instead of seeing the value before the change).
In reference to Scenario 2 above, Specman might miss the change on the VHDL signal since it is updated after the synchronization sample is taken.
To avoid both of these problems, the switch 'vhdlsync' has been added to irun/ncelab. In short, this switch separates VHDL process and Verilog always block execution lists. Thus, if you want to consider VHDL signal assignments to be treated as NBAs, and want Specman to sample the VHDL values just before they are updated, then 'vhdlsync' should be used. In such a case Specman starts synchronizing after the execution of VHDL process list and before it loops for more signal updates in the same simulation time (VHDL delta cycle increments), i.e. order of execution will be Verilog followed by VHDL and Specman gives consistent results irrespective of if it samples a signal in Verilog or VHDL.
Conversely, if this switch is not used, the order of evaluation is arbitrary, (as mentioned, there is no standard that specifies the order). Nevertheless, there might be many designs that count on that order (or should I say, “disorder”), and using 'vhdlsync' might change the behavior of their simulation. For example, consider the case where there are messages coming from different blocks at the same simulation time which may come in a different order. In this case the switch is not default, and both behaviors (with and without the switch) are supported, and "correct".
There are more details and examples where this switch can be required in Specman's Integrator's Guide, Chapter 13.4.6, "Mixed HDL Synchronization Issues”
Principal Support Application Engineer
Incisive & Specman Technology