Are you tired of putting print statements in your code to do
debug? Do you work with designers who
just want to use waveforms to debug testbench and design problems?
There is a cool feature in the OVM library and Incisive
Enterprise Simulator that comes to the rescue. It is the built-in OVM transaction recording.
Modern metric driven testbenches generate a lot of dynamic
data on the fly during a simulation run.
The test and testbench combination is usually simulated with multiple
random seeds to produce different sequences of transactions to maximize
stimulus variation to the design. When
the checker catches an error, there is always the question. Is it the design or the testbench? The answer usually is, let's look at the
waveforms to figure out if the testbench is doing the right thing.
Here you need a way to visualize and interact with the
transaction stream without modifying your verification environment. We want to get away from doing vector decodes
to figure out that this packet is going to port
5 or this transaction is a read request over a serial interface.
Using OVM with the Incisive Enterprise Simulator gives you a
built-in way to visualize sequences and transactions generated by OVM sequencer
without writing any code!
Consider the following class called xbus_transfer representing a CPU transaction. The steps in the
illustration highlight how transaction recording is automated via base class
functionality and macros that implement virtual functions.
class is used to create sequences of transaction in a verification environment
using ovm_sequencer base class. Typical
environments have a handful of random sequences that the user defines to
capture interesting scenarios using constraints on transactions. The user can use ovm_random_sequence to perform random selection of user defined
sequences or specify their own weighting or specific sequence selection for a
test. The following example shows how transactions
are automatically recorded during the simulation and their visualization by
using SimVision waveform window; these transactions are from the bus master and
use the ovm_random_sequence.
From the above graphic, let's figure out what happened.
On the left you see the sequence hierarchy. It shows that the top most sequence, also
called the default_sequence is set as ovm_random_sequence for this test. Upon expanding this stream (clicking on the
plus sign in the left frame next to ovm_random_sequence),
you can see what the ovm_random_sequence did during the simulation run.
In debug, it's helpful to correlate the sequence tree that
ultimately creates the transaction so you can review the sequence code and
adjust constraints if required. For
example, to see how the first random write occur, I can put the cursor in SimVision
anywhere on the transaction and immediately understand that the WRITE of size 1
to address ‘hE539 was caused by the following sequence chain:
--> request WRITE, size=1, addr='hE539
Using the GUI, you can easily correlate the abstract
transaction chain with transaction details, all by leveraging automation in the
Incisive Enterprise Simulator and the OVM library.
How To Control Transaction Dumping in a Simulation
Transaction recording is controlled by setting "recording_detail" variable at the component
level using the standard OVM configuration API.
You can control transaction dumping for any ovm_component or the derived class, through SystemVerilog test or
IES TCL command. Remember the ovm_sequencer
is a child of ovm_component.
Controlling recording_detail from IES TCL Command
The two above examples show different ways to enable the
The first one turns on transaction recording for
the specific component hierarchy "ovm_test_top.xbus_demo_tb0.xbus0.masters.*"
This includes all subcomponents under masters instance.
The second command uses the wildcard "*" to enable transaction recording for ALL components in the testbench. Wildcarding is very convenient to affect large portions of the design with a single command. However, care should be taken when using it in a large verification environment because it may create a lot of waveform data affecting simulation performance.
To turn transaction recording off using TCL, use OVM_NONE in place of OVM_FULL as value of recording_detail.
This command can also be used during the run to capture transactions in a time-window desirable for bug analysis.
Controlling recording_detail from SystemVerilog Test
You can use standard OVM configuration mechanism from your test's build method to control transaction recording dumping as follows:
Once transaction recording is enabled in a simulation,
transactions can be viewed by loading the waves.shm
database in SimVision interactively or in post-processing mode by selecting the
appropriate component from the testbench hierarchy and sending it to the
waveform viewer as shown below.
Some Practical Considerations
Enterprise Simulator and the OVM library ensure that changing "recording_detail" of a component
doesn't affect random values. This
way a failing random simulation from a regression run can be rerun with
the same random seed value with transaction recording, signal probes and
high message verbosity to speed up failure analysis.
api provides a better alternate to control transaction recording vs. the
SystemVerilog build() function
TCL doesn't require recompilation, any change to SystemVerilog test does.
TCL can be used to enable recording in a time window to speed up debug simulations
need to use the OVM library distributed with Incisive Enterprise Simulator
to take advantage of automatic transaction recording and TCL API.
Simply use "-ovm" switch with the irun script to pick up the OVM library
with transaction recording hooks into SimVision and OVM TCLcommands.
recording can be used in more applications such as displaying transactions
collected by monitor, showing cause and effect by linking transactions
traversing the design, and more.
For more information, see:
- xbus example distributed with the OVM library
- OVM Class Reference Manual, Component Hierarchy, Transaction Recording under <IUS install>/doc/ovm_ref
- OVM User Guide, XBUS OVC example under <KITSOCV install>/doc/ovm_guide
- OVM User Guide, OVM TCL Commands under <KITSOCV install>/doc/ovm_guide
NOTE: You can download KITSOCV and IES tools from downloads.cadence.com
If you have any questions, feel free to post a comment or email genIES@cadence.com.