Home > Community > Blogs > Functional Verification > Heads-up: Mixed Signal Verification Webinar (June 10)
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Functional Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Heads-up: Mixed Signal Verification Webinar (June 10)

Comments(0)Filed under: Functional Verification, verification strategy, AMS, Incisive Enterprise Simulator (IES), e, Specman, IES-XL, verification, Incisive

For those Specmaniacs using the REAL number data type & ports capabilities in Specman, you might be interested in a webinar our analog colleagues are hosting tomorrow (June 10) from 07:00- 8:15 AM (PDT) and a second broadcast at 10:00 -11:15 AM (PDT).  Specifically, the webinar is titled "How to Boost Performance for Mixed Signal SoC Top-level Verification", and it will address how to handle mixed signal design complexities that can create additional re-spins due to logic and functional errors, interconnect errors, polarity inversion errors, etc.  The presenters will also show how some new REAL digital modeling capabilities can be used to perform top level verification to achieve significant simulation mixed analog & digital domain performance improvements. 

Here is the link to sign-up:
http://www.secure-register.net/cadence/virtuoso_webinars

And here is a more detailed outline of the presentation:
* Cadence Mixed Signal Verification solutions addressing the analog and digital centric use models
* What is Real Number Modeling?
* Simulation performance vs. accuracy tradeoffs with real/wreal models
* Basic and Advanced real/wreal functionality included in the IES 8.2 release
* Detailed examples of Wreal Models, e.g. PLL, VHDL DAC, Analog Mux, etc.
* e & SystemVerilog Real to Electrical connections
* Provide examples of real to wreal coercion, wreal arrays, how to effectively develop a wreal table model, etc.

Hope to see you online!

Team Specman

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.