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Users Report on OVM in a Multi-Language World: Results From DVCon

Comments(0)Filed under: OVM, SystemVerilog, SystemC, e, OVM e, OVM SV, DVcon, OVM SC

The OVM user reports from Xilinx, SiRF, and ST at the DVCon luncheon were real engineer-to-engineer presentations, not the shiny presentations this marketing guy is accustomed to giving.  While my partners in blogging have reported on the OVM in a Multi-language World tutorial and luncheon, I wanted to follow-up with a few more details.


We just received the numbers from DVCon and it looks like 100 people signed in for the tutorial, though my count came to about 60 in the room at any given time.  Brett Lammers of Cadence and Jonathan Bromley of Doulos did an excellent job on the content and delivery as well as answering the many questions from the audience.  Among the questions were:

Q. Do existing eRM eVCs need to be upgrade?

A.  No, the OVM e library that was posted to OVM World is backward compatible with several new features as well.

Q.  Are the e and SystemC OVM libraries part of the OVM 2.0 download?

A.  Both the e and SystemC libraries are in the contributions area today.  Only the SystemVerilog library is in the OVM 2.0.1 download at this time.

Q. Show of hands - how many are using VMM?

A. About 50% of the hands went up.  (It's always nice to see how attractive the OVM is to new users.  :-) )


Rijwane Islam from Xilinx, Mohammed Haque from SiRF, and Greg Augier from ST Microelectronics joined Cadence's Mike Stellfox in presenting experiences with the OVM.  We had originally asked each one to present just their OVM (SystemVerilog or e) experiences, but each one went beyond expectations to set the OVM in context of their overall verification including functional coverage, planning and management, VIP, AMS, low-power, and multi-language use.

The four presentations are available here:

SiRF, ST Microelectronics, Xilinx, and Cadence.


If you have any question, please post them and I will ask the authors to respond.

=Adam Sheriblog


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