Originally architected for multiple languages, the OVM is now
available for all three standard languages used most commonly in
verification SystemVerilog, e, and SystemC. The e and SystemC libraries comply with
the OVM 2.0.1 methodology and are available as open-source on OVM
All Languages in One
Methodology - How?
The key to this all-for-one methodology is an architecture
built from the ground-up for multiple languages. Figure 1 shows the OVM Verification Component
(OVC) "agent architecture." The OVC contains the monitor, sequencer, and driver
which communicate among each other and outside of the OVC via a standard TLM
channel. This structure not only enables
reuse both within the OVC and among multiple OVC, but it also enables multiple
languages to be used because of the clearly defined, language independent APIs.
Figure 1: OVC Agent
The other key to the multi-language architecture is at the
environment level as shown in Figure 2.
By hierarchically defining the configuration of the overall environment,
the OVM can pass configuration information from the top-level in one language
to OVCs below in another language.
Figure 2: Integrated
OVM Environment with multiple OVCs
The architectural elements described here for multiple
languages were in place for OVM 1.0 in January 2008. The new libraries for OVM e
and OVM SystemC now implement OVM in the other two IEEE standard languages used
in modern verification environments.
OVM e - Addressing the Next Verification
Having introduced the agent architecture of the verification
component in 2002, eRM users currently enjoy the same methodology as OVM
SystemVerilog users. With OVM e,
users will get a new set of system level features in addition to the new
features that align the library implementations to enable easier multi-language
integration essentially making this the next eRM version. Specifically, OVM e improves sequences,
enhances performance, aligns base classes, aligns test flow phases, provides synchronization
with SystemVerilog and SystemC, enables the ability to reconfigure VIP, and
adds TLM ports. These changes add to the
so that existing eRM environments become OVM environments and users can
instrument their existing e-based VIP for use in
multi-language verification environments.
Cadence has applied this technology itself so that both SystemVerilog
users can take advantage of its portfolio of proven
OVM SystemC - Easing
TLM Integration with the Verification Environment
SystemC use is growing in many projects as design teams move
up in abstraction and seek better execution speed for the design under
test. The new OVM SystemC library aligns
base classes, aligns test flow phases, and provides the TLM API to enable
multi-language integration. The new OVM SystemC library also provides for
multi-language configuration to enable the hierarchical assembly of the
verification environment that enables the OVM to scale to system-level
This short blog only introduces the concept of the OVM
multi-language libraries and the top technical features of the OVM e
and OVM SystemC libraries. The actual
contribution on the OVM
World contains much more details in the actual libraries and user manual.
If you have any questions feel free to post them here, email them to firstname.lastname@example.org,
or contact your local Cadence representative.
We will have more information available shortly in webinars and
workshops so stay tuned to this blog for more on OVM for multiple verification