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DVCon 2009 - Day 3

Comments(0)Filed under: Functional Verification, Testbench simulation, Formal Analysis, verification strategy, DVcon, funtional verification

Today I was able to cover a paper on "OVM-based Methodology for Low Power Designs", and the panel titled "Mixing Formal Analysis with Simulation: Why, When, Where, and How?"  Click here for some annotated photos.

* Given there is much to say about the topic of Low Power in general, and OVM in specific, I felt authors John Decker and Neyaz Khan did a great job in compressing such an expansive subject into the presentation slot.  And given the great Q&A during and after the paper, it's clear that the interest in the topic is as high as ever.  As such, I plan to do a follow-up blog interview with John & Neyaz.  Stay tuned ...

* Interest in formal verification, and its relationship to traditional simulation techniques is also quite high as evidenced by the fact that people were literally lining up to ask questions of the panel.  Suffice to say, the experts on the panel -- including people from all the EDA vendors that sell formal tools plus customer representatives from ST Micro, Marvell, and Sun -- did not disappoint.  It was easily one of the meatiest panel discussions at this year's DVCon.


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