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Adaptive Chips Selects OVM Over VMM -- An Interview With Amjad Qureshi

Comments(0)Filed under: Functional Verification, OVM, eRM, CDV, SystemVerilog, VIP, e, Adaptive ChipsOn February 11 Cadence announced that Adaptive Chips had adopted the Incisive verification solution using the OVM to improve its verification process.  I had the opportunity to "virtually" sit down with Amjad Qureshi, Vice President of Technology at Adaptive Chips, to ask him a few questions about his project.
 
Amjad, can you tell us about Adaptive Chips?
I am currently the Vice President of Technology for Adaptive Chips Inc located in San Jose CA. Adaptive Chips is a Bay Area startup company focusing on multi-media silicon solutions. We also offer complete design services from Architecture to GDSII.
 
As a start-up, how are your verification challenges similar to, and different from, larger companies?
As a start-up, and given our business nature, it is vital for us to deliver fully verified design IP and integrate third party IPs. Our methodology enforces the use of internal and external VIPs that must be "best in class" and support multiple languages such as SystemVerilog, Verilog, C, SystemC, or e. Integrating third party VIPs can be very challenging and resource intensive which is why we believe that we carefully chose the methodology that best suits our customer needs, accelerates time to customer, and minimizes resource count. 
 
Given those challenges, how did you select the OVM?
We evaluated several verification methodologies, including VMM, and decided to go with OVM.  As I mentioned earlier, multi-language support is very important for us. We build many e based verification components and environments and I was in search for a verification methodology that supports e and class based SystemVerilog. OVM supports that very well. with OVM one can perform module, processor and system level verification under the same umbrella. Module and processor (aka cluster level) verification can be done using CDV [coverage driven verification] and e. System level verification can be done using class-based SystemVerilog allowing for HW-SW co-verification. The advantage here is one can use the same VIP across all verification levels. Re-use, Re-use, Re-use.  I don't believe in throw-away test benches or verification environments as they are waste of time and resource.
 
Interesting.  How does the multi-language architecture help you?
As I mentioned, we use SystemVerilog and e. Since OVM is architected for that it made it a natural fit for our needs. We also found out that VIPs are easy to develop and integrate using OVM. We need to access the best VIP and integrate it regardless of language as we can not control our customer's environments but we must ensure timely 100% coverage
 
As VP of technology, what would you like to see next in the OVM?
I like to see more OVM based VIPs available, more automation at all verification levels (Block, Cluster, System). It really should be "plug-n-play" for the end customer. I am a firm believer of "re-use" and would like to see environments reused across projects and all verification levels (horizontal and vertical). I also would like to see more support for HW acceleration and in-circuit emulation. Finally, I like to see more class libraries supporting software. With the advanced verification methodologies, we should be able to verify applications "efficiently" on RTL and support all abstraction levels for hardware and software.
 
Amjad, thanks again for your time.  And to our blog fans, if you have any questions for Amjad feel free to post them here or contact him off-line at amjad@adaptivechips.com.
 
=Adam Sheriblog

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