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Post-Show Thoughts on DesignCon 2009

Comments(0)Filed under: Functional Verification, DesignCon, DVcon, coreuse, NXP

Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and I'm finally finding a few minutes to comment on the event. I have a soft spot in my heart for this conference; I think that I've presented something in some form at every show but one since it was called Design SuperCon way back in the mid-90s. I agree with Joe that this is not a major conference for advanced verification folks, but I did meet some very experience verification and CAD engineers in the few hours that I worked in the Cadence booth.

I also attended several sessions, including an interesting panel on verification of low-power designs, and talked about what Cadence is doing with the NXP CoReUse methodology at a tutorial on this topic. Of course, as at any conference, a good portion of the value in attending is networking (and, for far too many this year, job-hunting) with industry colleagues.

If you can travel in for only one show, DVCon is a better bet for hard-core verification folks. But for those of us in Silicon Valley, it's worth checking out both shows. See you there next year!

Tom A.

The truth is out there...sometimes it's in a blog 


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