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Scalable OVM Register and Memory Package

Comments(9)Filed under: OVM, eRM, SystemVerilog, e, Register Package, vr_adDrawing on nearly a decade of experience, Cadence has just posted the first release of a scalable, open-source register and memory package for the OVM to the OVM World contributions area.  Modeled after the industry's first and most widely used "vr_ad" package for eRM, this new package is implemented in SystemVerilog but architected for multiple languages.  vr_ad is actively used by thousands of engineers worldwide and these e and SystemVerilog versions of the register and memory packaged will be merged in the future.  Along with the OVM package, Cadence is providing an IP-XACT parser so that verification engineers can use a standard input to manage registers and memory in complex OVM verification environments.

What is a Register and Memory Package?

A register and memory package is an important methodology extension providing additional observability and controllability in complex verification environments.  For example, in a typical processor-based system device registers are used to configure peripherals and are most often managed by the software running in that system.  For most modern systems, a directed test approach is out of the question so a randomized approach is needed to configure all of the system modes that need to be tested.  While the OVM is the ideal methodology in which to build the sequences and virtual sequences needed to verify the system, it still needs a way to reach into the DUT and configure the peripheral registers and system memory.  The register and memory package provides that access.

Requirements for Any Register and Memory Package

Any register and memory package must provide a set of capabilities to enable broad adoption.  First, the package must adhere to standards to assure the same interoperability as the host methodology.  Due to the complexity of modern systems, that means both the package itself and the register/memory descriptions that feed it must be open. Second, critical verification tasks including coverage, constraints, and back-door access must be automated to seamlessly integrate the package with the host methodology.  Third, the package needs to comprehensively support the SoC register types including direct, indirect, and mirrored.  Finally, the package must generate IEEE standard code leveraging the host methodology and scale to support hundreds of thousands of registers.

 Open, Scalable, and Infused with Experience

The customer-proven OVM register and memory package delivers on all of the key requirements.  Drawing from the success and momentum of the OVM, the package is IEEE compliant with the first implementation in SystemVerilog. Feeding the package are register and memory descriptions captured in the standard IP-XACT XML and a converter from XML to the package is provided with open-source deliverable.  Using IP-XACT is the open format defined by SPIRIT and assures multi-vendor interoperability of the register and memory descriptions.  Within the package verification engineers will find all of the critical technologies they need to manage registers and memory including coverage, back-door access, constraint management, sequence interfaces, single and multi-register manipulation, monitoring and more.  Maybe most important of all, the package is infused with more than five years of expert experience and has been validated by skilled verification users in live projects.

Getting Started, Deploying, and the Future

The OVM package is available and open for use today.  Cadence experts monitor the OVM forums, so feel free to post questions there or send direct questions to ovm_contributions@cadence.com for more personalized assistance.  Cadence and the OVM partners can also provide services and training to help you deploy the package in your group and company.  Consistent with the on-going evolution of the OVM, a few different packages are available on the OVM World contribution site further exemplifying the openness and vibrancy of the OVM ecosystem.  The OVM also has a proven track record of providing backward compatibility as it provides unified releases, so you can confidently adopt the Cadence OVM register and memory package knowing that your investment is protected while tapping the most experienced team and solution.

=Adam Sherilog


By AlokSharma on February 24, 2010

1) Can you please provide the link to the XML parser (for SV). I didnt see it in the register package (www.ovmworld.org/contributions-details.php)

2) The backdoor access mechanism is nice, but, I was wondering if it is feasible to have backdoor access to registers in RTL as well. That way the backdoor access is much more usable !


Alok Sharma

By Kathleen Meade on February 25, 2010
Hello Alok,

The reference link you provided is for the Mentor Register Package.  This package does not include an XML parser and I don't know about support for backdoor acess.  

Please feel free to download the latest Cadence OVM Register Package (ovm_rgm) from: www.ovmworld.org/contributions-details.php

It includes an XML parser at $OVM_RGM_HOME/builder/ipxact/ovmrgm_ipxact2sv_parser.jar

The backdoor access mechanisim is provided to do exactly what you would like.  It allows access to a register/signal directly in the RTL design via a hdl_path.  

Please have a look at the ovm_rgm package.

I hope this helps!


By Aleksandar Randjic on June 21, 2010
can you please answer to the following question:
- is this package going to be core of UVM one or not - if not, will you tune this one to be "UVM package compatibel" or you will abandon this one
- when e version of this package will be available - we do not want several reg packages in our mixed language DV VE
- will UVM version of register package is going to be there soon in e?
Thanks in advance

By Team genIES on July 1, 2010
Hello Aleksandar,
First, the Cadence OVM package has been converted to be UVM compatible and is available from the contributions area on http://www.uvmworld.org right now.
The Accellera UVM team (VIP TSC) is working on register packages right now.  That process involves collecting requirements from user companies like yours, combining them with vendor requirements like those extracted from nearly a decade of usage in vr_ad and the Cadence OVM package, and then determining which of the vendor packages best fulfills those requirements.  That process will culminate at the next Accellera UVM face to face August 3 - 5 at the Cadence Chelmsford, MA R&D site with a vote to follow in the next full TSC meeting.
All of that detail just means that there will be one UVM package identified by the middle of August.  The TSC will then work on implementing the missing requirements and is on track to publish the package by the end of October. The Accellera UVM roadmap is available on the UVM World site as well.
Once that package is determined, Cadence will align the e-based vr_ad.  The committee has already expressed an interest in making UVM multi-language and Cadence will continue to lead in that area offering a multi-language UVM similar to the multi-language OVM we introduced in February 2009.
Sorry for the long reply, but hopefully that paints a complete picture for you.
=Adam Sherer, Cadence Product Management and Accellera VIP TSC Secretary

By Jeff Schroeder on July 1, 2010
I can't find your UVM register package in the contributions area. I realize that your post is new as of this morning, but you did say that the package is there right now.
What am I missing?
Jeff Schroeder

By Adam Sherilog on July 21, 2010
Hi Jeff,
The UVM register package contribution can be found at: www.uvmworld.org/contributions-details.php
I apologize for the delay, but we were on holiday just about the time you posted your comment.
=Adam Sherilog

By Joe on September 27, 2010
2 questions:
Can you point me to an example that uses RGM for both registers and memories?
I can't find the source code for the Java utility, are you only partially releasing rgm to the community?

By tomacadence on October 1, 2010
Joe, please check the latest versions of the OVM and UVM packages to see if they have what you need:

By Joe on October 18, 2010
Thanks Tom, yep 2.4 has much better memory examples, sorry I didn't see that release before I posted.
I see the schema's components but no source code for building the jar file.  I guess if everything works that's ok but it is always nice to have a back up plan to present (i.e. "we can always fix it ourselves").
Thanks again for pointing me to the latest release and thanks to all the developers who are contributing to make life easier for us end users.

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