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Predictions for 2009

Comments(0)Filed under: Functional Verification, ISX (Incisive Software Extensions), metric driven verification (MDV), ISX, verification strategy, IES, System Verification, Multi-domain verification: HW/SW co-verification, HW/SW, Incisive Enterprise Simulator (IES), SystemC, Specman, OSCI

Having summarized the main verification technology-specific observations that the "Trailblazer" team saw in 2008, which to recap were:

1 - 1 billion logic gate chip roadmaps are here
2 - True "Metric Driven Verification" (MDV) starts to evolve from CDV
3 - The "language war" is over -- all languages won!
4 - Pre-silicon HW/SW co-verification became too important to ignore
5 - Analog+Digital verification frustration grows
6 - Low Power pain continues

I'm going to now make predictions for 2009.  However, to minimize future embarrassment, I'm going to limit myself to only 3. [*Deep breath*] Here goes:

Items 1-6 above only become "more intense" in 2009
Given all the sour economic news out there is a temptation to believe that all activity has stopped and the semiconductor market has gone into a state virtual suspended animation.  Granted, many of our customers have cancelled projects, but from what I can tell there is plenty of work to be done in the projects that remain, and many new projects that have been consolidated from the remnants of the old ones.  Hence, I predict we'll hear tale of over a dozen 1 billion logic gate chips be launched in 2009, which will mean items 2-6 above will all intensify -- and create growing opportunities -- in 2009 despite all the economic FUD.

ESL almost goes mainstream
With all due respect to industry analyst and long time ESL booster Gary Smith, I predict that ESL -- defined here as wide adoption of SystemC as a modeling, design, implementation, and verification language with a supporting ecosystem of EDA tools & methodologies -- will almost go "mainstream" in 2009.  Of course, the key words here are the definitions of "wide adoption" and "mainstream".  I'll set this "mainstream" bar as being 25% of all design code being done in SystemC vs. an RTL (like Verilog, VHDL, or SystemVerilog Design).  While SystemC and its ecosystem is definitely gaining momentum for all the reasons Richard Goering cites in his 2009 outlook article, RTL simply has too much inertia to be overcome to hit this 25% bar in 2009 even if innovative new products like C-To-Silicon Compiler continue to build momentum.  Still, having said all that: the increase in things like C-To-Silicon Compilier, Incisive Software Extensions (ISX), and even the venerable Specman-SystemC interface (whether inside Incisive Enterprise Simulator (IES) or OSCI SystemC) indicated to me that the "grill is warmed-up", and I'll hazard to guess that by the end of 2009 the SystemC+ ecosystem will finally touch the 10% adoption level by years' end.

IP management will become critically important
Being an engineer at heart, it's sure tempting to get caught up in the cutting edge scientific and technical challenges creating a 1 billion gate SoC.  However, one thing that keeps coming up in customer discussions on such chips is the conceptually simple, yet logistically daunting, task of managing all the design and verification IP for such a monster chip, PLUS the related simulation data, config files, constraint files, low power descriptions, make files, etc., etc.  Even worse: such monster SoCs typically have many possible configurations and derivatives that must also be supported simultaneously.  And of course, product teams are being asked to accomplish all this with the same-or-less head count that they had for prior projects. 

In a nutshell, this issue seems to be what's keeping my customers up at night the most (even more than low power fears!)  I'm tempted to wonder if this means that 2009 will be the break out year for emerging data management protocols like the XML-based IP-XACT, or growth in tools like Clear Case, but I confess I'm personally not a domain expert here (but fortunately for Cadence I have colleagues have very deep experience in this space -- I'd be happy to introduce you offline).

One final, bonus prediction for 2009 is really a theme embedded throughout this post and the 2008 review: despite all the economic FUD out there, I feel the outlook for the verification space is bright.  Think about it: even if the number of design starts  decreases, the number of gates to be verified (as consolidated into ever larger SoCs or large FPGAs), plus the HW/SW and digital-analog cases that need to be validated, only continue to increase.  Furthermore, this increase in verification state space often grows at a "more than Moore" pace given how IP state spaces can combine in a square law fashion.  In short, I suggest that 2009 could be a *growth* year for verification, and I urge you all out there in the verification world to prove me right!  ;-)


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