I'm excited to report that Tuesday's techtorial, covering a range of topics underneath the metric driven verification and OVM umbrellas, was a great success (Here is the detailed agenda for reference http://www.secure-register.net/flyer.php?id=260).
I make this claim not just because of the numbers (a 71% sign-up/attendee ratio -- much higher than the typical 50% you can expect in North America), but because this was easily one of the most interactive audiences of this size I've seen in awhile, where all of the presentations drew at least one good question per slide, with the Vishal & Kathleen's "Structured, Scalable Testbench" segment prompting the most Q&A.
Further proof that we piqued the audience's curiosity comes from the fact that 75% stayed for the afternoon workshops (vs. the typical expected falloff of 50%). All the credit for these great results goes to the Silicon Valley Field Team and R&D who really put their heart into inviting the audience, and making good on our invitation with compelling technical content.
Annotated photos from the event are here:
In case you missed the techtorial, the good news is that we are having free, follow-up "deep dive" events and workshops on some of the topics over the next few weeks:
* 11/11: Introduction to SystemVerilog and OVM workshop
* 11/12: Webinar on “IFV Productivity Flows”
* 11/18: Formal Verification workshop
* 11/20: Metric Driven Verification workshop
* 12/4: OVM with SystemVerilog workshop
You can register for any and all of these free events here on the main cadence.com events page.
Last but not least:
On behalf of the whole event team, allow me to thank the attendees! Your questions and discussions really enhanced the program to everyone's benefit, and the Verification Team looks forward to seeing you at these upcoming deep dive workshops!