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Putting a face on the OVM

Comments(1)Filed under: OVM, CDNLive, Open Verification MethodologyAs I recently blogged, there appears to be growing buzz over the Open Verification Methodology (OVM). Last week we saw two press announcements from companies (OKI and KPIT) realizing technical and business gains adopting the OVM.  By the way, since the OVM blog last week, we are now over 80 people in the LinkedIn OVM Professionals Network with more joining every day!
 
There are many more stories like these.  One great place to be face to face with the OVM community is at the CDNLive! user conference in Silicon Valley in September. If you can make it to the conference, you’ll have a chance to hear first-hand how some Cadence customers and ecosystem partners are putting the OVM to work for them.
 
In particular we are declaring Sept 10 as "The OVM Day" at CDNLive! (at least for functional verification!).  On Sept. 10, the sessions include “Converting SystemVerilog Testbench to OVM in One Day” (Marvell Semiconductor Inc.); “Into the Light: Embracing the Open Verification Methodology” (Magnum Semiconductor); “Benefits of OVM and SystemVerilog” (IBM); and “Creating an ERM-Compatible OVM UVC in SystemVerilog” (Verilab).
 
There will be plenty of additional opportunities as well to learn about the OVM. Are there any particular OVM-related questions or topics you’d like to see addressed at CDNLive!—or anywhere else, for that matter?
 
=Adam Sherilog

Comments(1)

By JL Gray on August 4, 2008
Adam, Just as an FYI, due to a scheduling issue we won't be able to present the paper "Creating an eRM -Compatible OVM UVC in SystemVerilog" at CDNLive! in San Jose.  Hopefully we can work something out for a future conference.  Take care, JL

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