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Upcoming Webinar: SoC Verification Challenges in the IoT Age

Comments(2)Filed under: verification, ARM, Cadence CEO, SoC, electronics design, semiconductor ip, ip cores, IP design, webinar

When it comes to Internet of Things systems, the name of the game is low power and small footprint.

This is often easier said than done in an environment in which designers must take those two huge issues into consideration while figuring out how to implement and verify low-power mixed-signal blocks into cost-effective SoCs and get to market before their competitors.

ARM and Cadence are hosting a webinar July 22 to explore just that: How teams can address Internet of Things (IoT) and (SoC) design and verification challenges in a timely and effective manner.

The webinar will focus on SoC implementation and verification using an ARM Cortex-M0 processor. The Cortex-M0 is ARM’s smallest 32-bit core, consuming as little as 16µW/MHz (90LP process, minimal configuration) in an area of under 12,000 gates.

This turns out to be especially useful for engineers migrating from 8- and 16-bit systems who are keeping their eye on efficient code use but want the performance enhancements that come with a 32-bit architecture.

Diya Soubra, CPU Product Manager for Cortex-M3 processors at ARM, and Ian Dennison, Solutions Marketing Senior Group Director for the Custom IC and PCB Groups at Cadence, will guide atttendees through ways to reduce time to market and realize power-performance-area design targets.

Click here to register.

Brian Fuller

Related stories:

--Webinar: Addressing MCU Mixed-Signal Design Challenges

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