Home > Community > Blogs > The Fuller View > tsmc symposium eda ip ecosystem primed for 16 10nm nodes
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of The Fuller View blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

TSMC Symposium: EDA/IP Ecosystem Primed for 16, 10nm Nodes

Comments(0)Filed under: EDA, FinFET, TSMC, finfet process, 3D ICs, IP blocks, advanced node optimization, 28nm, 20nm, 10nm, 16nm, IP libraries

SAN JOSE, Calif. -- 28nm may still be considered the mainstream node, but for leading-edge designers, there is a clear and compelling path from there through 16nm and into even the 10nm design ecosystem.

That was the message last week from Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC, who spoke at the annual TSMC Symposium here.

Whether it's design infrastructure (design rules, PDKs, reference flows, and so forth) or IP, TSMC has charted a course deep into the FinFET era that will take design teams well into 2020 and beyond.

Some highlights from Lee's presentation:

20nm

At this emerging node, DRM, PDKs, libraries, the IP portfolio, and design-for-manufacturing (DFM) design services from TSMC and its ecosystem partners is complete. "20nm is there and ready for you," Lee told the packed ballroom during his presentation.

16nm FinFET

Among other features, at 16nm, Lee said there is optimized low Vdd, "which has been a particular focus ... as one of the key enabling technologies for 16nm," Lee said. In addition, Vt min-area pessimism reduction has been factored into place and route, he said.

For DRC, TSMC has continued to enhance front- and back-end dummy fill. For LVS (layout versus schematic), the node features fin layer generation "to make sure we don't have any spurious problems during LVS time."

In addition, to improve design accuracy and PPA (power, performance, area), "we've enhanced capabilities to support 3D extraction."

When it comes to electro-migration and IR issues, TSMC has focused on both gate-level and transistor-level improvements.

For SPICE simulators, TSMC has poly-over-diffusion-edge (PODE) back annotation support and now has three fast SPICE simulators certified from the major EDA vendors.

When it comes to a 16FF reference flow for ASIC/SoC design, TSMC focused on FinFET solutions and methodologies to increase designers' PPA advantage.

"We focused on low-voltage design enablement, EM reliability, and power integrity management as we go into FinFET-based design," Lee said. "We also focused on timing analysis and silicon-accurate correlation," using the ARM Cortex-A15 processor as the qualification vehicle, he added.

For the 16FF custom reference flow, one of the things TSMC took into account was "rather than continuously variable gate widths, we now have a number of fins methodology where there are quantized fins available so we're focused on automatic fin snapping and fin placement, so you can ensure the design is correctly implemented."

Regarding the 16FF custom integrated tool flow: "We took a large PLL and ran it through the entire flow in the same manner one of our customers would. So we've gone through schematic design, simulation, layout, editing, physical verification, EMI analysis and, finally, RC extraction. 16nm FinFET full custom design is fully available and ready to go."

Digital integrated tool certification is complete for all major place-and-route tools at the 16nm node, which emerged a year ago, Lee said.

"We've used ARM Cortex-A15 to qualify all flows. We looked at single core, quad core designs. We've met our PPA targets using those tools. A lot of work was done by our partners, and we appreciate the effort."

16FF+

16 FinFET+ targets a 15% speed gain over 16FF by--among other ways--boosting DC Ion and Ioff, improving middle end of line capacitance and back end of line capacitance.

Regarding the design infrastructure supporting 16FF+, TSMC has expanded its certification program by adding new features to re-validate place-and-route accuracy as well as timing accuracy and EM and IR, Lee said.

He added: "A major task for us as partners has been to regenerate PDKs and tech files for DRC, LVS, and custom design support. The reference flows for 16FF+ have digital methodologies in place."

10nm

Work on the 10nm node proceeds apace, especially on double-patterning challenges.

Lee said, "The key process challenges for our EDA partners is the fact that the color A and B are systematically asymmetric on rules and performance so we have to support full coloring throughout the entire tool chain and make sure we are balancing proportions of mask A and mask B."

An example of this is the full coloring-aware design solution for place and route. "In place and route, we've got pre-defined coloring tracks to match up with pre-defined pins on cells, and this ensures we've got a balance of mask A and mask B. Furthermore, we have co-optimized cell design and placement again to improve pin access and to ensure we have mask balancing," Lee said.

"Since we have asymmetrical behaviors in terms of resistance variation, we have timing optimization to leverage different wire resistance between masks," he added.

"We've implemented color-aware design throughout the entire tool chain," he added.

IP readiness

As for IP cores across the node spectrum, much of the infrastructure already is in place, with the availability of 6,600 IP titles from 39 vendors, Lee said. "It continues to grow as we move from process generation to process generation," he added.

At 28nm, "virtually the entire" IP portfolio is ready to implement.

At 20nm, most of the portfolio is ready, with PCIe IP coming in June, Lee said.

"At 16FF and FF+, the message is 'the portfolio ready,'" Lee said.

For more information visit TSMC's technology page.

Brian Fuller

Related stories:

--TSMC Forum: 16nm FinFET Design Challenges Met by Custom/Analog Reference Flow

--TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support 

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.