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The Road to 1 Million Tapeouts

Comments(0)Filed under: Cadence, EDA tool vendors, EDA tools, Brian Fuller, design automation, electronics design, EDA software, ip verification, ip cores, ip vendors, IP design, Martin Lund

MONTEREY, Calif.--One million tapeouts a year.

When Cadence Senior Vice President Martin Lund uttered those words with a smile on his face, the small crowd at an industry event here chuckled knowingly.

They chuckled because they know it would be a great number to achieve, and they chuckled because they know the road there is not smoothly paved.

"My vision is, let's get to a million tapeouts a year," Lund said April 18, during a keynote address to the Electronic Design Process Symposium. "That would be a good thing." 

Design Complexity, Market Pressures

A good thing for the industry indeed. And it seems achievable, especially the potential scale offered by markets such as the Internet of Things.

But how does the industry get there? How does it get there amid increasing design complexity? How does it get there with relentless time-to-market pressures? How does it get there with ever-present cost pressures and a much faster pace of innovation?

Lund (pictured, right) described a road map (link to his presentation), and his message was that the industry gets there by rethinking old notions, considering system design more holistically, and by delivering IP and EDA tools to get the job done. 

It starts with a new outlook: a system-level mindset. 

"Are we thinking about the point problem? Point products? We need to bring to bear system-level thinking to solve all aspects of the problem. If you don't think about it up front, you don't design to constraints and you end up with something that doesn't work or can't be built at a reasonable cost." 

We're firmly entrenched in the era of cores-based design and, fortunately, much of the work that once consumed design teams--designing to ever-changing industry protocols and specs--has been assumed by third-party IP. This allows teams to focus their design value on the core of the system.

Adding Design Value

And here is one area where system-level thinking and design trade-offs need to be considered.

For example, designing a core in RTL is generally considered up to 1,000 times more power efficient than other approaches, Lund said. 

But there are tradeoffs: 

"The trick is to find balance between the optimization (benefits) of RTL, which means that it might be the best possible implementation, but it takes a long time to verify and bring to market, and, once you've written it, it does not change." 

A team designing for the smartphone market might consider the power demands of a system that awakens to voice command (in other words, the system is never really asleep).

That's useful functionality for users, but if implemented in software running on a dedicated processor, that functionality might quickly gobble up the battery.

A programmable solution, by contrast, might offer much better power efficiency, he added.

Speed, Agility

And then there's the ever-present time-to-market pressure.

Said Lund: 

"There's a lot of competition, and competition drives innovation. It's the fuel for innovation. And one of the artifacts is time to market. The guy who takes your market window takes all your dollars. If you're third, fourth or fifth, it's not a very good business to be in." 

As teams embrace system-level thinking, they must consider the application software that will run on top of the hardware.

Lund said:

"Software is what stands between us, our chip and money. If your software doesn't run, it doesn't matter whether the chip runs. It's only when the software is running that the value is there."

And that means--especially with the specter of time to market--that software needs to be part and parcel of the design from the very start and verified hand-in-hand with hardware. This, of course, not only speeds design completion but helps teams optimize both hardware and software along the way.  

Lund said: 

"There's a difference when people say ‘I have it passing in RTL' and ‘I have it running on an emulator.' Once you put it close to the real hardware (in an emulator), you're forcing all the elements to come together earlier." 

On the Road

Another challenge to getting to a million tapeouts a year is that, given the emerging market potential (especially in IoT) and almost infinite number of possible applications, it's not going to happen on common platforms.

Lund said: 

"A lot of these brave new world applications require implementations that are innovative to fulfill the platform. To make a Fitbit (health-monitoring bracelet) into a ring and have it be alive for 30 days, there is no standard product you can build that's optimized for this. You'd get around to building the ring as a standard product and then someone will want it as an earring. Because power is king in all of these applications, you can't build common platforms that hit all these things."

This requires an innovation ecosystem that leverages partnerships, IP, tools and methodologies along with the system-level thinking. Fortunately, we've begun to build that ecosystem to meet the challenge, Lund said.

"Today's SoCs require even more collaboration across the industry and the ecosystems. While we are heavily competing in the marketplace with each other, we're also part of an important ecosystem for the world, and it's a unique opportunity at a place like this to form bonds and collaborate."

Brian Fuller

Related stories:

--Martin Lund's EDPS presentation

--Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says

-- Mobile World Congress: Martin Lund on IP and Electronics System Design

-- Why Cadence Exhibits at Mobile World Congress and CES 2014



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