With nearly a quarter-century of experience in the IC packaging and co-design markets, Kevin Rinebold (pictured below) has a perfect perch from which to discuss issues and trends in board design. One of the more crucial issues today is how to manage the growing complexity of designs across chip, package and board. With higher pin counts and more high-performance interfaces, failure to properly plan and account for the PCB during chip floor-planning will result in a needlessly complex system that comes up short against performance and cost targets. Rinebold, senior product marketing manager for IC packaging, SiP, and co-design solutions at Cadence, discussed some of challenges in this Q&A:
Q: Kevin, let's talk a little history. What's changed in packaging in the past couple of decades?
A: In some respects, not too much. In others, things have changed significantly. Packaging still serves as the mechanical enclosure, manufacturing form factor, and thermal conduit for the silicon it encompasses. But today, signal and power delivery have a significant impact on the PCB layout. This is driven by the sheer number of signals moving through the package, along with decreasing noise margins and supply voltages. Today's BGA-style packages have a significant impact on PCB layer count, route complexity and cost. Efficient BGA net assignment and patterning of power and ground pins can make the difference between a four- and a six-layer PCB.
Traditional methodology for chip-package-board design has been a serial top-down flow where the chip drives package connectivity and, in turn, the package drives board connectivity. With more functional integration taking place at the chip- and package-level, package pin counts continue to grow to a point where several thousand pin packages will not be uncommon.
Q: That's significant complexity. How do design teams need to address this without getting overwhelmed?
A: Well, some companies have moved to a more coordinated approach with emphasis on early planning between chip, package and board.
Q: So, if everybody follows in line, problem solved, right?
A: Well, not quite. This approach is limited by use of separate implementation tools and databases: one for the chip, a second for the package, and a third for the board. As a result, most collaboration is done using spreadsheets to communicate pin assignments and plan interfaces. While a step in the right direction, it's still a less-than-optimal solution. Spreadsheets are snapshots of static data that do little to facilitate real-time planning or improve efficiency, nor do they scale well with the increasing pin count and complexity.
Q: I know spreadsheets are effective, but there have to be more productive approaches, right? Are there technical hurdles? Cultural hurdles?
A: Most companies and their engineers recognize the value of a coordinated design methodology across chip, package and board, but face both technical and non-technical obstacles to fully realize the benefit. It doesn't make much sense when a packaging team produces an initial bump pattern and I/O pad ring placement only to have the IC team discard it and recreate the results because of the data format. That happens more often than you'd think. While the data format was an issue, the behavior has more to do with the silo culture found in some companies where design remains an over-the-wall process. Within their respective silos, groups are too consumed with tasks at hand to recognize a need to change. A tipping point is fast approaching, driven by package pin counts and high-speed interfaces where increased effort and manpower alone will not be enough, unless accompanied by a change in culture and methodology.
Now consider fabless semiconductor companies. They rely on outsourced semiconductor assembly and test (OSAT) companies for packaging. The fabless companies have a mechanism to provide initial die data - typically in some form of a spreadsheet. As the number of constraints associated with high-speed interfaces continues to grow in quantity and sophistication, this communication and exchange mechanism must adapt.
Q: You've talked about "multi-fabric" planning and how it can be applied to improve design in these situations. Can you give us some additional insight?
A: Multi-fabric planning coordinates chip, package and board planning, and it's more than a change in methodology. It necessitates new tools and flows capable of delivering a multi-fabric view of the system hierarchy, while providing simultaneous access to domain-specific data like macro placement, I/O pad ring devices, bump patterns, ball pad assignments, and placement of critical PCB components and connectors.
This planning tool needs innovative functionality to manage and manipulate a range of multi-fabric data at various stages of completeness, and adapt as portions of the design become less abstract during the planning process. Integration and usability are crucial to minimize disruption, while still providing fast ramp-up for casual users. The major components of multi-fabric planning include system definition, bump/ball pad patterning, connectivity planning and net assignment, and interface planning.
A fundamental aspect of multi-fabric planning is the ability to quickly make placement and net changes in one fabric and immediately see the impact on adjacent fabrics. This requires an environment capable of uniting design data of various sources and formats for the purpose of planning, then communicating the data back to the respective implementation tools for completion.
Q: So where do teams start with multi-fabric planning?
A: They start by establishing the physical relationship between the chip, package and board. In other words, establishing the full system representation. This is accomplished using hierarchy management to establish and manage the relationships among the fabric. It enables representations of the complete system from the chip-level to the PCB, while maintaining the integrity of individual design fabrics. Most every aspect of planning and exploration will reference the hierarchy before performing a given task.
Think about incorporating an advanced package onto a PCB for a consumer product driven by cost considerations and performance. While device placement and assignment decisions made solely in the context of the chip may yield the ideal chip-level design, they could ultimately result in missing the cost and performance targets for the end product. In such a top-down system flow, the chip-level placement dictates the bump and ball assignments in the downstream fabrics. This could result in excessive coupling in the high-speed memory interface and a needlessly complex escape routing scheme that requires additional layers in the package and PCB substrates.
Q: Obviously planning in this complex environment is key, but engineering teams often use planning tools from what seems like a long-gone era.
A: Just as spreadsheets were the old way of communicating pin assignments, tools like PowerPoint or Visio were the choice for interface planning or as means of communicating design intent. Used to sketch out and visualize a route plan, they quickly lose usefulness as the number and complexity of interfaces and signals increase within a design.
Today's high-speed interfaces require careful planning across multiple devices and fabrics to ensure proper performance. Interface planning helps drive pin assignments, flow and location of major busses, and evaluates interaction with other interfaces and signals within the system. It provides flexibility to work at a coarse level to establish initial placement, then refine down to the individual byte lanes as a plan emerges. Interface planning is made up of three major steps: interface definition, floor-planning and flow planning.
Multi-fabric planning that unifies chip, package and PCB to facilitate bottom-up planning is a more efficient path to product realization.