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EDA Verification, IP Innovation Drive System Design: Taneja

Comments(0)Filed under: Cadence, EDA tools, EDA companies, electronics design, computer design, ip cores, ip vendors, chip design, IP design, Sanjiv Taneja

SAN JOSE, Calif.-- The old model of innovation "just doesn't work" anymore, and EDA vendors are stepping up their own innovation to keep systems designers more efficient and productive.

That was the message from Sanjiv Taneja, Cadence Vice President of Product Engineering for Front End Design, who addressed the Silicon Valley Open Innovation Summit here April 2. 

"It's very clear that ... the traditional innovation model is under complete stress," he said (see slide, left). 

Enabling Faster Exploration

One of the focuses of EDA today should be to provide tools to free system architects to allocate their time optimally--where appropriate and valuable--on the complex, time-consuming task of detailed micro-architectural specifications, but leaving the vast majority of innovation at the algorithm or system level, Taneja said.

He said:

"In this world of a disaggregated design chain, the one thing as a system designer you control is the architecture. It's completely under your control. You can bring all the underlying ideas and algorithms to bear."

The key question becomes how do you enable the system architect to explore algorithm ideas quickly, "in a time frame of relevance," Taneja added.

There are a number of ways, both at the implementation level and at the verification level, he argued.

At implementation, stepping up the abstraction ladder from RTL to transaction-level modeling -- what industry analyst Gary Smith has dubbed Electronic System Level Design -- brings enormous productivity benefits.

Taneja said:

"You have to rise up to the next level of abstraction...RTL to TLM and describe your function in System C and let high-level synthesis technology help you explore the solution space in a very comprehensive and convergent manner."

He noted those benefits were partially behind Cadence's decision this year to acquire Forte Design Systems and its TLM and SystemC technologies. Taneja (pictured, below right) acknowledged that while TLM has yet to hit the mainstream, it will win over engineering teams soon because of the flexibility and agility it offers. "Any time there is a shift (in abstraction), like from gate level to RTL level, there are compelling benefits," Taneja said.

By writing at the TLM level, verification teams are "abstracting away the micro architecture," writing 4X fewer lines of code and improving verification speed and effectiveness by 5X.

The Verification Challenge

After implementation, when it comes to determining whether your design is going to work properly, challenges continue to abound. Said Taneja:

"The verification and validation challenge continues to rise very significantly ... because you are integrating an unprecedented level of functionality as you move from one process node to another."

The "old models" that Taneja described referenced the serial fashion in which hardware and software were designed for systems, one before the other. Today, complexity and time-to-market challenges make this a nonstarter for the vast majority of designs.

There are a number of pre-silicon verification approaches that can improve productivity and cut time to market, including virtual prototyping, emulation and FPGA prototyping, each with its speed and flexibility benefits, he said.

IP is Key

Taneja also delved into the productivity gains inherent in smart IP reuse.

He cautioned that IP should fit your SoC, not the other way around. He likened the smart IP reuse approach to an automated IP factory that customizes and generates IP based on system requirements and application needs resulting in a sum that is far greater than the sum of its parts.

The last piece of the puzzle is analog-mixed signal integration in the presence of low power, where complexity has risen quickly in recent years. And "it's not just a few analog blocks interacting with digital but it's a whole slew of mixed-signal blocks that have in turn their own digital and analog pieces with complex power management schemes," Taneja said.

Here it's important to work in a comprehensive verification environment, one that leverages formal verification techniques formerly applied only for low-power digital designs . At heart of that is "to be able to do a macromodel of the power intent so that the proven techniques of digital low-power verification can continue to be applied," he said.

Brian Fuller 

Related stories:

--Gary Smith Webinar: “The True ESL Flow is Now Real”

--ISQED Keynote: How RTL Synthesis Must Change for Advanced Node Designs

--Q&A with Nimish Modi: Going Beyond Traditional EDA

  

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