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DVCon 2014: How to Close the Verification Gap

Comments(0)Filed under: EDA tools, verification, electronics design, EDA software, Richard Goering, system design, software-driven verification, JL Gray

SAN JOSE, Calif.--Sometimes in the electronics industry, the best questions are at once the simplest and scariest. Consider the one raised in a DVCon 2014 panel (Richard Goering blogged in detail here): Have we created the verification gap? 

I invited Cadence Senior Architect JL Gray and ChipDesign Magazine Editor John Blyler to join me at our DVCon video studio to frame the question. After all, Gray conceived the panel and Blyler moderated. 

Gray decided to take things up a notch by proposing additional--and unsettling--questions:

  • Are we creating methodologies that cause it to be harder for us to verify our designs?
  • Are we creating verification teams that are too big?
  • Are our methodologies not always applied in the right areas?

Here's what the two gentlemen had to say:

Related stories:

--DVCon 2014 Panel: Did We Create the Functional Verification Gap?

 

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