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Sealing the Seams in System Design

Comments(0)Filed under: EDA, Fullerview, Frank Schirrmeister, hardware-software codesign, embedded systems design, design engineering, DVCon, CDNLive

Our Cadence colleague, Nimish Modi, SVP of Marketing and Business Development, has called them "seams": gaps that emerge as electronics system design gets more complex. These seams occur when teams focus on components of the larger electronic system design. Yet how can they not focus, given the relentless increase in complexity?

Get out the glue

One answer emerged at a DVCon panel March 5: The "glue engineer," a brilliant and energetic traffic cop of sorts who oversees and understands the implications of all aspects of the design verification and can arbitrate disputes. But that traffic cop—even if he's called a system architect—doesn't really exist today.

Take, for example, Frank Schirrmeister's anecdote. Schirrmeister, Cadence's group director for product marketing of the System Development Suite, quipped that it's not uncommon for members of a given company's hardware and software design or verification teams to meet and exchange business cards. DVCon 2014 software and verification panel

Speaking on Semiconductor Engineering Editor Ed Sperling's DVCon panel (pictured, right), Schirrmeister said:

"Do we need a new generation of engineer? A new person who is deep enough to do both [hardware and software verification] because I don't see the software guys moving... and I don't see the hardware guys [moving] because they're both so busy, they're focusing on their  individual problems."

Ken Knowlson, principal engineer at Intel, has a ringside view to the challenges:

"What I'd like to think are systems engineers ... are more like ‘glue' engineers. The glue is to know enough about the specific firmware to take it and modify it and work with the design guys. I can get the architects early, but getting people who actually know the code to participate early enough? It's always going to be a challenge." 

But Sandeep Pendharkar, vice president and head of product engineering at Vayavya Labs, who participated on the DVCon verification panel with Knowlson, Schirrmeister, and others suggest progress is being made: 

"Some customers take a pragmatic approach. One of the gentlemen with whom I've been talking has actually hired three software engineers to be part of the design verification team. All that these software engineers do is they just write device driver code in C. The verification engineers then sit with them to understand it and, if required, create an equivalent System Verilog for that side of things."

In many ways the onus for managing this problem may fall to EDA vendors, according to Schirrmeister.

That "glue person" needs to "know enough about both sides to be dangerous and to challenge a bluff from the hardware or software side that it's not their problem. But we as EDA vendors need to provide the environment that you can do that efficiently from both sides," Schirrmeister added.

There is opportunity where those seams, as Modi has called them, emerge. But it is in increasing design services, as one reporter asked Cadence CEO Lip-bu Tan at a March 11 CDN Live press session?

Tan wasn't asked directly about the need for glue engineers or seams, but he said: 

"Would the customer need help in design? Absolutely. Are we going to build that business? Not now. We shift a lot of design services into IP. We help them tape out on time and on schedule. Clearly design services needs to tie into IP."

And while it may not be that design services per se is the answer, it falls most likely to EDA companies to fill these seams and, in effect, become the glue engineers of this emerging era of systems design enablement.

Brian Fuller

Related stories:

--2013: Quickening the Pace of Electronics Innovation?

--DVCon 2014 Panel: Did We Create the Functional Verification Gap?

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