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DVCon 2014 in Review: Formal Verfication, Value Chain, and the Industry's Future

Comments(1)Filed under: EDA tools, Lip-bu Tan, Cadence CEO, Jim Hogan, EDA vendors, IC design, chip design, #semieda, DVCon

Venture Capitalist and EDA luminary Jim Hogan (pictured, background, left) may have put it best during his Tuesday luncheon presentation when he said DVCon probably has outgrown its space at the Doubletree Hotel in San Jose. This once-sleepy but focused event was the watering hole for a relatively small band of verification engineers tackling bleeding-edge problems. DVCon2014 Jim Hogan at Cadence luncheon

But as verification continues to consume more design time and the challenges—especially at advanced nodes and with 3D and FinFET structures—escalate, more verification engineers are attending and are being joined by more design engineers.

Hogan, in an interview with me, described some of the challenges when he said the design value chain is breaking and needs to be reconstituted. Partly this is due to the verification challenges at advanced nodes and with 3D and FinFET structures; partly it's due to the demands of hardware-software co-design: We no longer can design complex SoCs and systems in serial (hardware then software) and expect to get to market in a reasonable timeframe. So codesign is the obvious approach, but how do we verify as we go? How do we manage that complexity?

The System Perspective

Cadence CEO Lip-Bu Tan in a keynote presentation described how non-traditional engineering customers at the system level are engineering their own systems and SoCs, and changing the EDA/IP value chain as they embrace this.

Those were some of the views from above, if you will. On the ground, a packed poster session on Tuesday featured informal presentations from a host of EDA vendors and their customers.

Richard Goering corralled two Cadence colleagues, Jose Barandiaran and Bin Ju, to talk in separate interviews about two approaches to formal verification (see below).

Jose Barandiaran on using formal approaches to verify security keys:



Bin Ju on applying formal methods for SoC connectivity: 


We'll post more highlights from DVCon 2014 in the coming days, so stay tuned.

Brian Fuller

Related stories

Lip-Bu Tan at DVCon 2014: EDA/Silicon Ecosystem Crucial to Innovation

VIDEO: VC Jim Hogan on EDA, System Design's Future



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