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Lip-Bu Tan at DVCon 2014: EDA/Silicon Ecosystem Crucial to Innovation

Comments(0)Filed under: Lip-bu Tan, Cadence CEO, design automation, EDA vendors, electronics design, IC design, chip design, IP design

Social media and apps developers such as WhatsApp (which Facebook bought in February for $19 billion) succeed on the shoulders of EDA, IP and semiconductor companies, which aren't valued as highly. This is a message that Cadence CEO and longtime venture capitalist Lip-Bu Tan has offered for some time.

And at this week's DVCon 2014 in a keynote address, he returned to it--with a twist. As the pace of innovation changes and quickens, a new breed of customer is embracing the value of the EDA, IP and semiconductor design ecosystem by building their own components and subsystems with their own engineering teams.

That represents enormous opportunity for the electronics design chain, Tan said. But at the same time, engineers still face the verification bottleneck, slowing their path to market, and vendors need to work diligently to ease this bottleneck. Cadence CEO Lip-bu Tan keynoting DVCon 2014

"It's exciting to see all these systems companies starting to appreciate the semiconductor's importance," Tan told a packed ballroom at DVCon. "What you do and I do is so important to them in terms of the services they want to provide us (as consumers)."

He added that any stall in innovation from EDA and silicon vendors hampers the growth of social media and other similar companies, and they realize it.

That's why it's crucial that the industry continue to innovative along multiple vectors and work to reduce the amount of design time taken up by verification.

Increased Complexity

With increased system-on-chip complexity comes the need for more silicon-proven, quality IP blocks--much more. Tan shared industry data that indicated at the 90nm node, an SoC contains an average of 18 IP blocks. At 14 nm, that's expected to be 123 blocks, a nearly 20 percent jump from the 22/20nm node, according to the data.

He cited the 4X complexity increase frrom DDR1 to DDR4, 2X increase from AMBA AXI to AMBA ACE and similar jumps from Gen 1 to Gen 3 of PCI Express.

"Clearly increasing complexity isn't stopping. It's compounding even more," Tan said.

Referencing the increasing importance of software as a key part of system design, Tan noted that verification remains a bottleneck for engineers, occupying in some cases 80 percent of total design time.

"One of biggest bottlenecks is verification and that's why we're all here, trying to figure out what are the solutions," he said. "I've always believed as engineers, the more challenge there is, the better we are."

Tan mentioned metric-driven verification as one approach to tackle verification complexity in a systematic way.

The other way to confront increased complexity is to move up in abstraction from RTL to TLM, not just for design but also verification.

He referenced Cadence's recent acquisition of Forte Design Systems as an important move in this direction:

"I've been watching the company for nine years. I thought it made sense to move to the next level. A lot of customers see the benefit of it."

System complexity and time-to-market pressures also mean that hardware-software codesign and coverification "become very real," Tan said, adding system-level analysis today "is critical."

"Not just semiconductor companies, but systems companies are moving down and they expect that (system-level approach). A lot of customers are engaging with these tools. That's where we have to respond to time-to-market pressures."

He closed with a call for the industry to work together to lure more teenagers into electronics. He also said, "With all these drivers, and the technology challenges, let's make it exciting to do innovative things."

Brian Fuller

Related stories:

--Interview with Lip-Bu Tan, Part 1 – How Cadence is Positioned to Build Upon Success

--Interview with Lip-bu Tan, Part 2: Energizing the Electronics Industry

--Cadence CEO at DAC 2013: 'I've Doubled, Tripled Down on Semiconductor Investment'


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