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Interconnect IP Experts Answer Your Design, Verification Questions

Comments(0)Filed under: Cadence, Electronic Design Automation, EDA tools, Top EDA companies, EDA companies, verification, design automation, electronics design, semiconductor design, IC design, semiconductor ip companies, interface design, computer design, IP blocks, memory ip, ip verification, ip cores, interconnects

When it comes to electronics design and interconnects today, chaos is king. As the capacity of systems on chip soars, so too do the number of intellectual property (IP) blocks used to realize the design. And as that happens, the interconnection of the fabric and its verification rises in complexity and consumes more electronics design time.

Cadence ip verification live chat

As Hao Wen and Jianhong Chen of Spreadtrum and Dave Huang of Cadence wrote recently

"The traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient."

 

Part of the answer came last week when Cadence launched its Cadence Interconnect Workbench, which

  • Provides a graphical performance analysis capability that helps system architects run what-if experiments quickly with different interconnect configurations
  • And automatically generates a verification environment that includes a UVM e or SystemVerilog testbench, configures VIP that applies stimulus and response to the interconnect, and builds a verification plan that tracks coverage metrics

Live Chat

Another part of the answer comes Wednesday Nov. 6, at 11 a.m. PST, when we host a live online chat with interconnect experts. The team will discuss the functional verification and performance analysis challenges posed by advanced interconnect IP. They'll explain how the Cadence Interconnect Workbench and Cadence Interconnect Validator can be employed to successfully address the challenges.

This is a great venue for you to submit questions and get direct, immediate answers from our panel of experts:

  • Tom Hackett, product marketing director
  • Nick Heaton, distinguished engineer
  • Dimitry Pavlovsky, staff solutions engineer
  • Avi Behar, product marketing director
  • Steve Brown, product marketing director

There's more information on the live chat here and you can click here to register. And check out the archived memory IP live chat we hosted in September here.

Brian Fuller

Related stories:

-- Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

-- Live Q&A with Memory IP Experts

 

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