emergence of 16nm FinFET process technology opens a world of promise to
electronics systems wrestling with Moore's law. It also comes with its share of
Consider exploding design-rule
complexity and skyrocketing resistance. Then there's the "silent
killer:" the difficulty for routers to connect efficiently to pins on
standard cells amidst the quagmire of conflicting and complex design rules.
And there's the challenge of
extracting parasitics from FinFETs, which is significantly different from
regular planar CMOS devices—all without growing old in the process.
Paul Cunningham, Cadence vice president
R&D and Azuro co-founder, and Rachid Salik, vice president of R&D at
Cadence, addressed these challenges in a presentation on October 1 at the annual
TSMC OIP event here in San Jose.
"The 16nm FinFET process has
presented an awesome challenge for us," said Cunningham.
Wire delays have been dominated by increased
net resistance, while net capacitance has remained relatively constant, and at
16nm, it's only getting exponentially worse, he added.
Hence, the effective use of
low-resistance upper metal layers (M9/10) to buffer timing-critical nets is
vital to achieve good timing closure. The wire delays of these upper metal
layers can be 10 times less than those on the lower layers, resulting in a big
timing gain from routing long/critical
nets on these upper layers, according to Cunningham.
"However, there are a limited
number of routing resources on these upper metal layers due to the presence of
power/special nets, which restricts the assignment of signal nets, and causes
potential congestion and routing issues down the line if not precisely dealt
"What is needed is a
route-aware optimization engine that identifies long timing-critical nets,
performs an accurate congestion analysis to make sure there is space available
on the upper layers, and then re-buffers these nets on the upper layers to
Optimizing in GigaOpt
Cunningham called out the
GigaOpt route-driven optimization technology in the Encounter Digital
Implementation System. GigaOpt is a multi-threaded, ROI-driven optimization
engine that provides optimal performance, power, and area, while accelerating
"We look at the entire solution space to optimize the critical net.
We evaluate different strategies, and for every strategy, do a cost analysis.
What's the impact of timing and congestion? What are the resources that are
available? What are the area and the power costs? Anything we do must converge
in the flow."
And as if there aren't enough
metrics to be concerned about, please welcome pin access as a new critical
design-closure metric (see images nearby).
techniques-—critical to ultra-deep submicron fabrication—are leveraged to get
the maximum possible density of tracks in lower metal layers.
But this makes it harder to undertake
graceful via spacing and via cuts.
"It's getting harder and harder to cut them close together. You
get a larger and larger halo around each via cut before we can cut a
neighboring via. If we're trying to turn a corner on the same layer, to escape
from a via then we have to have a certain minimum distance. We can't turn a
When it comes to pin access,
it's going to be very hard "to via down to the pin. As you via down to one
pin, you're going to create a halo that locks pin-access to the neighboring
pin," Cunningham said.
This and other complexities can
make it "just incredibly difficult to get the design to route. The
congestion... can be low but if your local pin density gets out of hand, the
design won't close, it won't route."
"As a result, careful control of
pin densities during cell placement, and global pin-access planning during
detail routing, can have a big impact on achievable design area."
The extraction challenge
And then there's extraction at
First off, you have to build
electrical models that will represent parasitics on the FinFET. And then those
models have to be compact to minimize design-turnaround time.
There are challenges
with FinFET that we have to address:
- Establish and extend FinFET RC
parasitic models to be closer to those extracted using a field solver (2.5D
- Compact RCs around FinFET not to
explode design TATs
- Convergence between pre-layout
and post-layout by generating good-estimation parasitic RC models of FinFET
"It's one thing to
accurately model RCs, but if we have to explode the design time by 10X, that's
not an efficient way to do it," Salik said.
Cadence is also driving
towards giving FinFET designers an earlier estimation of RC impact to converge
their designs, reducing the gap between pre-layout and post-layout.
"Designers can no longer
afford to assess the impact of parasitics after layout. Early simulation during
schematic design in the Virtuoso custom design platform or in the optimization loop
of the Encounter digital platform is required," he noted. This means tight integration of signoff extraction models of those implementation platforms.
"Moving to 16nm FinFET means more functionality on the chip. So we
had to work on extraction side to not be the bottleneck at signoff—mainly how
we can improve runtimes and build other methodologies like incremental
The 3D nature of FinFETs raises
capacitance challenges; in fact from 28nm to 16nm, capacitance increases 25
"We have to extract an
accurate model but extract it in a compact way," Salik said.
"There is the electrical interaction, capacitance between gates
and how we connect to transistors. The poly is also a 3D device, so all of
these bring a bigger challenge to accurately extract capacitances."
Salik said the "obvious
solution" is to build a field solver, but runtimes can be slow.
"So we have to extend our
2.5D models to be almost 2.9 to be as accurate as a field solver and to keep as
extraction runtime as low as possible compared to 28nm," he
Another key is to bring the RC
of the FinFET into a designer's platform as early as possible, since RCs have
twice the impact on delay at 16nm as they do at 20nm.
Cadence has been working with
TSMC on some reference flows in which the RC estimate within the FinFET is
segmented, "so you have an early estimation of the design parasitics to
reduce the gap between pre-layout and post-layout," he added.
Workshop—a Review of FinFET Parasitic Extraction Challenges
2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies