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What Do Applications Dream About?

Comments(4)Filed under: Cadence, EDA tools, Tensilica, EDA companies, The Fuller View, Brian Fuller, design automation, Chris Rowen, computer processor, computer architecture, multi-threading, multithreading, semiconductor design, multi-core, IC design, integrated circuit, semiconductor ip, semiconductor ip companies, memory controller, microprocessor design, computer design, IP blocks, memory ip

If you look back over the past two decades of processor-architecture design, you could say the period is defined broadly by two things: 

  • A vastly greater degree of design freedom
  • The ability to dream bigger dreams

Chris Rowen, the founder of Tensilica and now, since Cadence's acquisition of Tensilica, a Cadence Fellow, used the phrase in the title with that evolution in mind. The ability for "applications" (i.e. design engineers) to dream big today is directly related to today's design freedom.

Rowen described all this in a presentation before the Linley Processor Conference 2013 in Santa Clara (Oct. 16), during which he touched on the 10th generation of Cadence's Tensilica Xtensa data plane processor architecture. The architecture was first rolled out in 1999 and the water that's roared under the bridge since then has been quite a sight.

Evolutionary road

Back then, the company's initial product was "a rather narrowly defined set of extension and configuration options on top of a conventional five-stage pipeline 32-bit RISC machine," he said in an interview.

Back then, a typical core CPU might have comprised two-thirds of the final processor.

Today, that core is a fraction of what the final processor is, and Xtensa is a completely different animal.

Rowen said:

"We're created much more freedom in letting each SoC team define their architecture to fit the applications.This allows much more potent highly parallel architectures, so that the base 32-bit core is often just a few percent of the final processor."

Up the chain

This comes against the backdrop of a breathtaking but nevertheless logical evolution of system design in recent years. Moore's Law's effect on functional integration means successful electronics companies move up the food chain a little bit to deliver more value to their customers and capture greater margins.

So whereas cores vendors once were a cog in a big churning wheel, increasingly they're defining rather complete subsystems and making big contributions to the full-chip requirements because of all the hardware and software functionality they deliver. 

Their customers, in turn, are defining system requirements for their customers.

Seen in that light, Xtensa, 10 generations on, is a vast superset of what it was, all built along this degree-of-freedom road. And it addresses, among other things, the four "pinch points" in data-intensive processing today:

  • Memory hierarchy bandwidth and latency
  • Energy efficiency
  • Instruction set flexibility
  • Ease of software development

Problem solving

Xtensa 10 and Xtensa LX 5 (Tensilica's 5th generation SIMD/VLIW extensible processor) attack these problems with:

  • Memory subsystem improvements, including improved L1 cache performance and better PIF latencies
  • Low-power optimizations including power shutoff, data gating and EDA optimizations
  • And improved debug and ease-of-use, including better multicore and AMBA-based debug

Said Rowen:

"The level of sophistication and optimization in the compilers, the models that are generated, the kinds of bridges to on-chip interconnect, the automatic characterization of the performance characteristics of a given core and software in a vertical area--it's hugely enriched to make analysis and optimization and configuration as quick and complete as possible." 

Up the food chain, engineers in the software-defined-everything era we're in are increasingly relying on this functionality to build their systems. It's the stuff that applications dreams are made of.

Brian Fuller

Related stories:

-- We Need to Move "Past EDA": Tensilica Founder Rowen

-- Q&A: Tensilica Founder Chris Rowen - Perspectives from an IP/SoC Pioneer

-- IP Cores: How to Get There from Here



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