Every time I look at the ITRS roadmap I get a little queasy.
In five years, the average design is supposed to have twice the number of logic
gates alone (north of 300 million).
At the same time, we're supposed to double design productivity (and, presumably
churn out more complex ICs because the world will continue to demand them).
Seems Herculean doesn't it?
And yet, it will happen. Why?
Consider Cisco's "mega ASIC" that EE Times' Rick Merritt reported
on recently. The nPower X1 is a 4 billion-transistor chip that supports
400Gbit/s aggregate throughput.
400G chip sets in core routers from Alcatel-Lucent and others, Cisco crammed
all the packet processing and traffic management jobs—including packet
buffering, queuing and scheduling—into a single whopping 598mm2 die made in
a 40nm process.
Cisco believes the silicon integration gives it an edge in
packing Terabit/s throughput into a single linecard using an undisclosed
number of nPower ASICs. The top-end NCS 6000 systems using the chip and
shipping today claim 5Tbits/s throughput per slot and 1.2Petabit/s at the
So that roadmap isn't as crazy as it sounds. Consider that
this is an ASIC that leverages a lot of IP; it uses, for example, 336
dual-threaded Tensilica cores in part to achieve that blazing speed.
That sounds like a lot of work, but when you're leaning on
that many cores—quickly customizable in almost any way you can imagine—you can
see how we'll get from here to 2018. At its core (so to speak), this is a
design-efficiency IP choice.
But there's also the performance case to be made. Most
processors are hamstrung by the load-store bottleneck. Tensilica, on the other hand, allows FIFO-like data
streaming through its environs, which is a big plus in network processor
designs that are aspiring to 400Gbit/s speeds.
The approach is having an impact in other
processing-intensive SoCs. Consider AMD's TrueAudio technology in its R7 and R9
graphics ICs, which leverage three Tensilica
HiFi2 EP DSPs.
Carl Wakeland, a Fellow Design Engineer at AMD, told
Tensilica Xtensa HiFi EP provides single and double precision floating-point
assistance for calculating accurate simulations of the intended audio
environment. Compute resources from the GPU or CPU pipelines are not required,
and that's the intention of AMD TrueAudio: 100 percent offloading to preserve
or even improve system performance, even with superior audio.
Whether it's a customizable piece of IP or a core that's
more of a standard product, we're moving down the road at a decent clip,
despite the soaring complexity.
Indeed, when I chatted with Tensilica founder Chris Rowen earlier this year, he, as he usually does, articulated design evolution this
"I do believe as the semiconductor guys have
to move up and up in abstraction—they really are building the cell phones, they
really are building the networks, the server farms, they're building things way
up in that hierarchy—the question of the chip architecture can and should be
left more and more to efficient suppliers who are able to fill in the
There, I feel better now. My stomach's settling down.
Need to Move "Past EDA": Tensilica Founder Rowen
- Q&A: Tensilica Founder Chris Rowen—Perspectives from an IP/SoC Pioneer