SAN JOSE, Calif.--If you're the world's largest
foundry, there's no slowing down, especially if you're roaring down the road to
the "silicon wafer-based silicon super chip."
That was my take-away earlier this week (Oct. 1)
listening to TSMC Vice President of R&D and CTO Dr. Jack Sun during TSMC's Open
Innovation Platform® (OIP)
event here at Cadence headquarters.
From 20nm system-on-chip (SoC) production, to the ramp of 16nm
FinFETs, to 7- and 5-nm technologies in the distant future, and R&D and
capacity investments in between, the pace of innovation at the Taiwanese
company seems faster than ever.
in the driver's seat
Part of it involves the requirements to keep up with
power, performance, and area expectations that are higher and more intense in a
system-design era driven by mobile devices.
The other is that the industry's rapid
congealing around design ecosystems puts pressure on everyone--foundries, IP
providers, EDA vendors, design-services companies, and the design chain in
general--not to let others down.
No pressure there!
In an ironic twist of phrase, Sun (pictured here at an earlier event) told his
audience of 1,000+ engineers: "We need each other to be competitive and we
need each other to win."
Here's where TSMC stands today, racing down the
road to the future:
SoC: The 20nm ICs have been qualified for ramp, according to Sun. Customer
product chips have been delivered successfully-the same product chip with good yield from
both GIGAFABsTM in Hsinchu and Tainan, he added.
Sun told the audience:
"We continue to drive power, performance, and area scaling very
aggressively. From the performance standpoint and power standpoint, on an
annual basis we can give you more than 15% performance improvement at constant
power. For the same speed--compounded annually--we can reduce your power by 20
FinFET: TSMC already has achieved better than its target yield on this type
of device, Sun said, adding that performance of ring oscillators is "nearly on
target." The company already has completed an ARM® A57 test chip, with fMax on
spec, according to Sun.
"The reference flow, EDA, and IP ecosystem are
ready," Sun said.
Beyond that--beyond the work underway on 7nm and
5nm technologies (process R&D alone is $1.5 billion a year)--there's the
journey to the "super chip," as Sun put it.
The journey's underway: TSMC already has
demonstrated vertical 3D capabilities in the form of its chip-on-wafer-on-substrate
technology (CoWoSTM), which was introduced and tested out a year
ago. The technology uses silicon interposer technology to connect multiple
homo- or heterogenous ICs.
TSMC has demonstrated a CoWoS package with SoC,
embedded stacked DRAMs, and third-party Wide I/O DRAM integrated together.
A technology called advanced integrated fan-out
wafer-level package (InFO WLP) is a lower-cost and less-dense "cousin"
of the silicon interposer, which has qualified WLP for production.
"These are real. We can integrate billions
of transistors with a few hundred thousand microbumps," Sun said.
Thickness in packaged form can be as little as 250 microns, he added.
"That's ideal for future mobile computing
devices," he said.
-- TSMC 2013 Symposium: Progress in
20nm, 16nm FinFET, and 3D-IC Technologies
-- TSMC 2013 Symposium: Morris Chang
Overviews Semiconductor Market, TSMC Progress