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Tackling Complexity at the System-to-Silicon Verification Summit

Comments(0)Filed under: EDA tools, Top EDA companies, verification, Brian Fuller, semiconductors, Gary Smith, Jim Hogan, Gary Smith EDA, system on chip, SoC, electronics design, semiconductor design, Silicon Signoff and Verification, IC design, signoff, EDA software, Fuller View, semiconductor ip, validation ip, microprocessor design, VC investment, memory ip

System-to-silicon verification is the biggest challenge our industry faces today. It's also the biggest opportunity for both design teams and EDA vendors.

Consider the productivity and time-to-market improvements that we could yield in the coming years if everything goes according to plan. (In fact, it has to if we're going to cut the ratio of engineers per million gates-designed four fold in the next eight years as predicted by the ITRS roadmap). Verification remains the biggest chunk of the design process, but new technologies and methodologies are conspiring to whittle that down.

Relentless Complexity

verified hardware and software system At the same time, customer needs are getting more complex (see image, right, of major system and SoC development tasks ). No longer are we focused solely on computing and communications-infrastructure devices. There's a burgeoning new world of consumer electronics and mobile devices that demand high performance with miserly power consumption in tiny footprints to satisfy consumer tastes. Think Google Glass. Think the Pebble watch.

But then there's also the relentless innovation in larger systems: medical devices, games platforms, electric vehicles, and electric smart grid utility infrastructure and display technology.

New markets pop-up all the time and the rate of change has never been faster. Take automotive electronics for example: 15 million cars are produced every year, and in-vehicle networks have 10-100 end points. More than 100 million tablets ship every year, and millions more smart phones. And the then there's the Internet of Things: The total available market for this staggeringly huge machine-to-machine world is estimated to be in the trillions of units in the coming decade.

Verification Summit

To give electronics design engineers a sense for the challenges and some solutions that are on the horizon, Cadence is hosting a System-to-Silicon Verification Summit Thursday at its San Jose campus.

In this content-packed day-long event, we'll hear about verification challenges and solutions across the system-to-silicon design spectrum.

Among the questions we'll explore:

  • Yes, we know there is an obvious need for more verification cycles, but what can be done to make verification smarter?
  • With the increasing software workloads, is simulation acceleration running out of steam? If so, what do we do?
  • Ten years ago, design teams were much larger than verification teams; today verification teams are about the same size as design teams. How will this mix evolve in the next 10 years?
  • How do you determine the efficiency of hardware-assisted verification to legitimize the investment?

Beginning at 9:30am Thursday, these and a host of other questions will be fielded by a number of industry experts, including:

  • Charlie Huang, senior vice president, R&D at Cadence
  • Jim Hogan, EDA visionary and long-time industry investor
  • Brian Bailey, engineering consultant and EE Times design line editor
  • Kent Goodin, executive vice president, engineering, at Zenverge
  • Vik Singh, senior system software manager at Nvidia
  • Gary Smith, chief analyst of Gary Smith EDA.

To learn more about the events send an e-mail to events@cadence.com. To register, go to the summit event page and click on the register link.

Brian Fuller

Related stories:

--Palladium XP II—Two New Use Models for Hardware/Software Verification

--Designer View: Why We Used Specman for FPGA Verification

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