If you're a design engineer trying to navigate the world of
changing intellectual property (IP) standards and how this affects your electronics system and
subsystem designs, you have some choices:
Ask your boss for a month off to bone up on all
the new specifications, features, and functions and get current
Lay your head softly on your desk and whimper
Join us for a live
online Q&A Sept. 17 to get a firm grasp on the situation and boldly go
forth into your next design-specification meeting
I don't know about you, but No. 3 sounds the most reasonable to me.
Cadence has assembled a half-dozen experts in memory IP and verification IP to
chat about the challenges and solutions and answer your questions live and online.
It's a great way to hear directly from domain experts and get immediate answers
to your pressing questions.
Consider the changes in just the past decade (graphic, right): The rise of
several interface standards such as PCI Express, USB, Ethernet, ARM's Advanced
Microcontroller Bus Architecture (AMBA), and the Double Date Rate (DDR) memory
interface have become universally deployed standards.
This is all well and good, but consider that the DDR
standard itself, which was a single specification in 2000, has blossomed to 15
today. The ripple effect on design and other interface standards is enormous. And
that's just the DDR standard. This obviously affects everything from system and
subsystem design consideration to verification strategies and tactics.
Cadence Product Marketing Director and an expert on verification IP, wrote
extensively about these challenges recently.
Hackett will host our chat session next Thursday. He'll be
Raghavan, a Cadence fellow, who is responsible for areas including IP
roadmap development, SoC integration, and performance evaluation
Elsasser, a DDR IP architect at Cadence, who has more than 15 years of
experience in design and architecture of SoC subsystems
Kasamsetty, Cadence product marketing director, who focuses on memory design
Jacobson, senior product marketing manager at Cadence, who focuses on the
memory model portfolio and Ethernet protocols
Adams, director of the Cadence R&D Memory Model team
Q&A will begin at 11 a.m. PDT Sept. 17 and run for one hour. The
session will be archived as well. Register today.
We look forward to seeing you on the chat!
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