SANTA CLARA, Calif.--Just a few hundred yards from twisting and turning amusement park roller-coasters, Martin Lund took his audience on another thrill ride on Tuesday morning: a journey through the state of today's semiconductor memory business.
For decades, that semiconductor memory business--primarily DRAMs and SRAMs--was driven by one main application computing--primarily PC computing. Even with that architectural predictability (faster, denser, smaller), semiconducdtor memory prices went on roller coaster rides because of the commodity nature of the business.
Semiconductor memory fragmentation
Now, new electronics applications--particularly mobile--are causing architectural fragmentation in the semiconductor memory industry, said Martin Lund, senior vice president of research and development for Cadence's IP Group. And that is creating new "optimization points" where memory players a crucial role in systems design.
"Memory is truly a system-optimization challenge, meaning that you can't think of it as a discrete optimization point," Lund said here during the kickoff keynote to MemCon 2013 at the Santa Clara Convention Center. Take mobile designs, for example.
"Mobile comes with different optimization points. It's not just about capacity. It's bandwidth, power, capacity. Power is the no. 1 constraint point."
And into this turbulent environment comes a number of approaches, each optimized for certain benefits, but none validated as the path forward: Wide I/O, Wide I/O 2, DDR3, DDR4, 3D stacked dice, and hybrid memory cube architectures. Lund shared a slide (image, right) that illustrated trends in memory model downloads in recent years.
Each brings opportunity. Each brings challenges. Take 3D-IC approaches to memory--or what Lund called "non-monolithic integration." On the one hand, "It opens up a number of new system-optimization opportunities," he told the audience. "But it's much, much, much more complex. The domain of optimization is incredible."
Business model challenges
There are thermal constraints beyond just the packaging level. There are signal-integrity constraints: how do you probe that signal on a 3D device? And then there are the not-inconsequential business-model issues.
"Who pays for the stack of memories when one of those has a bad bit?" he asked. "How do we prove who is it who has to pay for the whole thing when something goes wrong?"
And while there are enormous challenges confronting the semiconductor memory industry today amid this explosion of architectural choices, progress will be made, Lund insisted.
"There are challenges, but the dollars going into the industry and importance of these challenges means they're going to get resolved," he said.
For example, adoption of 2.5- and 3D memories is "going to happen," Lund said, because of physics.
Semiconductor scaling imperative
"It's the nature of physics. It's about the cost of transporting bits," he said. "You can't rely on Moore's Law to scale. That is a fundamental reason things are going to happen."
At the same time, the answers aren't going to come from a single source, and the industry won't make progress without cooperation.
"The total solution is required...you can't do all by yourself. What's required is multi-domain optimization. Most people don't have all the skills from system modeling to signal integrity. You have to rely on partners, you have to rely on experts, whether that's hardware/software codesign, analog-mixed signal, analysis tools, signoff, DFT. All of these things have to come together."
And, of course, it's got to be cost effective.
Outside the convention center here, in the distance, not far from Lund, his presentation and an attentive audience, the roller coasters thundered away.
--Wide I/O 2, Hybrid Memory Cube (HMC) – Memory Models Advance 3D-IC Standards
(Here's Martin Lund being interviewed at MemCon 2013 by ChipEstimate.tv's Sean O'Kane):