Nearly 20 years after Mark Bohr's shot heard-round-the-world on interconnect scaling and circuit design, Paul Franzon is trying to sound the all-clear. Sort of.
Bohr, you'll recall, stood up at the International Electron Devices Meeting and presented his famous circuit design paper "Interconnect Scaling - The Real Limiter to High Performance ULSI."
In it, Bohr, now an Intel Senior Fellow, wrote that to combat scaling's detrimental impact on circuit design--specifically RC delay--"new conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements."
Today, we're at the dawn of the 3D-IC age in circuit design, and academics like Franzon (pictured at Cadence, right), an engineering professor at North Carolina State, are exploring the frontiers of what interconnects will be like after the "end of silicon scaling."
"We can continue exponential scaling through the use of technologies that are ancillary to CMOS transistor," Franzon said during a July presentation at the Cadence theater in San Jose.
And, in a nod to Bohr's three-decade-old circuit design paper, he added, "And better design will also enable continued scaling."
What kind of circuit design?
Going vertical is one of the paths.
To illustrate circuit design issues, Franzon showed a slide comparing on-chip gates times bandwidth to off-chip signal pins times bandwidth. The on-chip trend has traditionally doubled every 16 months and is now doubling about every 30 months. But where the off-chip had doubled every 28 months, that has now staggered to every four years, essentially flattening out.
"The reason for that is as FO4 (fan-out of 4) stops scaling, it's getting harder and harder for us to increase the data rates power effectively as we go off chip. And pins are expensive-we can't just add pins."
In looking at the 3D-IC interconnect, however, some benefits start to bubble up, especially in the area of energy usage. Data storage and communications take up big chunks of power, such as DDR3, which Franzon estimated consumes 4.8 nano-Joules/word. A SERDES I/O consumes 1.9 nJ/word.
But processing itself takes up very little, he pointed out. A 0.8V 45nm FPU consumes 38 pJ/operation and a through-silicon via (TSV) I/O takes up just 2 pJ/word.
"It takes more power to take the same word off the chip than it took to do the computation," he said.
Interestingly, when you move to 3D-ICs, the relationship flips.
"Doing 3D I/O to a stacked chip takes a lot less power than the computation," he said.
This reduces the power of the interconnect, but "it also means that if you get some other advantage by moving the data vertically...then it's worth doing that because it doesn't cost a lot to do it," he added.
Franzon also teased some research his team will publish later this year that shows long-range interconnect scales worse than computation elements. Looking at the improvement from 45nm to 7nm, Franzon said interposer I/Os and PCB I/Os improve just 15 percent in terms of energy consumption per 32-bit operation.
"In contrast, the purely computational aspects got 3.6 times better," he said. "This issue is difficult now. It's only going to get worse toward the end of the roadmap."
Additionally, another Sematech-funded study he ran found that in modeling a variety of interconnect models, "as you go from LPDDR3 to an interposer-based solution, you get roughly a factor of two improvement in power efficiency." He noted that as you move from interposer approaches to a "truly 3D-based solution," you get an additional 8x improvement.
"Yes, interposers are going to serve quite a useful purpose for a while. But 3D-IC with TSV has a significant fundamental long-term advantage that we'll be exploiting for quite a while."
We'll check back in another 20 years.
--Taming the Challenges of IC Design
--Archived Webinar: Variation-Aware Analysis for Advanced Node Design
--TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies