AUSTIN, Texas--You want the bad news first or the good news about IC design challenges?
Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity.
The good news? Electronics-industry collaboration and creative solutions are emerging that make tackling those IC design problems achievable, and EDA employment should remain robust for decades to come.
That was my take-away from Anirudh Devgan's SKY Talk at the Design Automation Conference here in June.
Devgan—Cadence's corporate vice president for R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group—is an implementation, signoff, and simulation guru of sorts in the IC design world. Before he joined the EDA community, he spent a dozen years at IBM in research positions in this area and holds a PhD in design automation from Carnegie Mellon.
So he knows his stuff. But even for old EDA industry hands who have confronted and then overcome seemingly insurmountable problems in the past, the future can be freighted with uncertainty. Devgan sees at least half-dozen major challenges ahead:
- Issues surrounding double patterning
- Layout dependencies
- Effects of the explosion of design rules (DRC)
- Static timing analysis accuracy
- Signoff closure
"The biggest new problem from an EDA perspective for FinFET design is the parasitic design challenge," he told an audience of about 150 people here. "There are lot more capacitances that are layout dependant that need to be modeled."
Additional extraction challenges emerge thanks to FinFET transistors and some newer memory structures.
"It's an important area and is ripe for innovation given that most of extraction was done by simple kind of table look-up models or a slow field solver-based method," he said.
"How many elements are you producing that effect circuit simulation? If one extractor uses fewer elements than others, that's a significant difference," he added.
While EDA companies and IC design companies have been addressing this challenge in the past few years, "it's only going to get worse" at 20nm and below and "with triple patterning or whatever else comes in the future," Devgan said.
The main IC design challenge is that it's difficult to predict DRC errors with double patterning. It isn't just a matter of flipping a shape (see chart below).
And design teams need to think about the ripple effects throughout their entire IC design, Devgan said.
"The impact is there for digital, analog, and mixed-signal design, but it's much more critical for custom layout," he said.
The finer nodes also increase layout dependency challenges, he said, including:
- Well proximity effect
- Poly spacing effect
- Length of diffusion
- Oxide diffusion (OD) to OD spacing
- Layout patterning check
- OD/poly density
"The criticality of these things is increasing rapidly," he said. "All these things have to be modeled correctly in the devices." (Read this related white paper for additional insights on some of these design challenges).
Design-rule checking challenges are "exploding" as something on the order of 5,000 design rules often need to be taken into account, at 20nm and below (double-patterning alone requires 30 to 40 rule checks, he noted). Some of these include L/W and varying transistor proximity as well as new rules regarding legal interdigitation patterns.
In addition, new routing layers (local interconnect and middle-of-the-line) allow very dense local routing but their consequences need to be understood.
Static timing analysis (STA)
STA affects things like margin requirements, clock trees, and dynamic voltage scaling but is starting to run into fundamental accuracy limits, Devgan argued.
Waveform effects at 20nm and 16nm as well as operation at lower voltages—particularly in FinFETS—"makes the problem a whole lot more analog," he said.
Lastly, signoff closure remains a challenge at advanced IC design nodes (see chart below), particularly as the number of timing views is increasing along with the margin and variations.
More optimization is being done in the signoff phase, which requires multi-step flows for extraction, timing, and optimization. Often 10 to 30 design loops are required and the time to timing close is often measured in weeks. Indeed, analysis and fixes in timing closure now consume 40% of overall design time, Devgan said.
But while these challenges are significant, they're not unsolvable. For example, "signoff, because it is the last step, has to be able to fix, not just analyze. There has to be more optimization there," he said.
Path-based analysis is one approach to improving productivity. Where graph-based analysis trades accuracy for speed, path-based analysis can decrease design pessimism by as much as 3% while sacrificing some runtime speed. Alternatively, if pessimism is not a huge concern, PBA can be used to recover 5% or more in power, Devgan said.
Devgan called for a new custom methodology that better links schematic with layout because circuit design cannot be done without knowing the physical implementation and implementation cannot be done without understanding the manufacturing implications.
"The key thing is to make sure we can tie this together without impacting the designer too much. If the setup of the tools takes longer than you can do the design then these things don't tape out."
Devgan described the notion "in-design signoff," a new approach that's required because extraction, DFM, and physical verification for advanced nodes shouldn't be treated as just a sign-off step. This is largely because the layout engineer has an additional hundreds of complex rules to manage at 20nm, Devgan added.
Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy
DAC 2013 Panel: What's Needed to ‘Fix' Timing Signoff?
Taming the Challenges of 20nm Custom/Analog Design