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FinFETs and Analog Design: Challenges Ahead

Comments(2)Filed under: FinFET, TSMC, DAC 2013, analog, Synopsys, finfet process, GlobalFoundries, finfet advantages, mixed-signal automation, Freescale Semiconductor

AUSTIN, Texas -- Electronic design with FinFETs is a raucous, excited conversation at the moment -- if you're a digital designer. If you're on the analog side, the conversation is a bit more measured. And in some cases, there are more questions than answers.

Is analog design even compatible with a 3D structure? If it is, what are the challenges, the drawbacks and the benefits?

A panel here at the 50th Design Automation Conference (June 6) tackled some of the challenges confronting the use of analog technology in FinFET-based design. Moderated by Altera editor-in-chief Ron Wilson, the panel featured:

  • Scott Herrin, analog design engineer with Freescale Semiconductor
  • Richard Trihy, director of design methodology and design enablement with GlobalFoundries
  • Navraj Nandra, senior director of product marketing for analog IP with Synopsys
  • Eric Soenen, academician director, TSMC.

What follows are some highlights of the hour-long session, starting with Wilson's straightforward tee-off question: Is analog usable in FinFETS? That was a good spot to throw it to the resident analog expert, Scott Herrin.

Herrin: There are things I see and get excited by. There are also things I get concerned about.

FinFETs and Analog panel: (L-R) Ron Wilson (moderator); Scott Herrin (Freescale); Richard Trihy (GlobalFoundries); Navraj Nandra (Synopsys); Eric Soenen (TSMC).

 FinFETs and Analog panel: (L-R) Ron Wilson (moderator); Scott Herrin (Freescale); Richard Trihy (GlobalFoundries); Navraj Nandra (Synopsys); Eric Soenen (TSMC).

The obvious ones are the ones most interesting to me. The increased gain, reduced leakage. The circuit possibilities that pop up are good. The negative things that are the easy softball answers are, OK, you have now a quantized transistor, you don't have the full range of W and L that you can work with. In analog design this is one of the areas we were probably a little too loose with to begin with. On analog side of the world, we'd be better off paying attention to what matching structures we have, what quantization we might use to stay a little closer to a model.

Trihy: We kind of have no choice. Scaling's reached its limits. To get beyond 20nm we need a new transistor. We believe there are advantages with higher gain. We believe there are going to be fewer short channel effects, to reduce variability, which is a big win for digital designers and analog designers.

We are working with EDA vendors today for developing solutions for designing with analog FinFETs. We are developing analog designs at GlobalFoundries for test chips so we can learn what the limitations are.

Nandra: The next question is, what are the advantages you're seeing with this new technology? What we've seen...is you certainly get better matching. The gain, if you look closely at the devices, is generally lower but intrinsic gain ... is better, and that's what analog designers care about.

Because of higher gate capacitance, there's lower fT and fMax. Knowing those parameters you can design interesting circuits.

...If you look at a D/A converter, the matching is better. And if it's a design that uses current sources, you can make those current sources smaller. So in FinFET technology your D/A converter is smaller in, say, 20nm. And analog engineers always say when you migrate to the next technology node things don't always get smaller. This is an example of where the D/A has gotten smaller because of better matching on current sources.

Q: Are we at a point where models are really accurate for precision analog design? Secondly, are the models practical in large-scale simulation or do we need new simulation algorithms and server technology?

Soenen: The tools are going to have to be smarter. The parasitics are going to be a little harder to simulate or extract, and the models themselves need to be a little more refined. That means of course we're going to have to throw at little bit more CPU time or CPU power at the simulations using FinFETs. But the good news is that CPU time is not that big of a deal. And the technology provided by EDA vendors, the simulators, are making a lot of progress too.

Herrin: At this point the response has been fairly positive that, yes, we will be able to have models. And I agree with everyone that we will absolutely have models that we will be able to use. Critical thing is going to be me looking at it from the analog designer side -- the differences. This is a new device -- the parasitics that we're looking at, the capacitances that we do care about -- those are going to be critical differences that we have not handled before going from planar devices. We're going to be relying much more heavily on our EDA support, our analog support.

Q: What kind of changes may we see beyond on what we just talked about?

Nandra: I mentioned earlier the higher gate capacitance. You can address that. You can basically adjust the fanouts. Another comment that was made and is true is about the quantized devices: We've developed some automation to convert the devices into the equivalent number of fins and the equivalent number of FinFET devices. If your simulation gives you a certain aspect ratios and it doesn't fit the grid, we've got a little utility to take that and quantize it.

Trihy: With 14nm, because of the quantization of the FinFETs, layout synthesis becomes much more practical. A lot of the solutions that the vendors put forward today to address the stress and interconnect challenges revolve around getting early versions of the layout for the blocks so it can be brought back to schematic as a better predictor of what the final performance will be.

Q: Some other companies have taken the path of extremely thin SOI, and they are claiming that this is a good alternative compared to FinFETs. Do you have comments about that?

Soenen: The whole idea is to put more transistors in smaller area. The density comes from second-order effects that we didn't have to worry about. I don't know whether ultra-thin SOI is going to be easier to model or easier to design with than FinFET. It's going to be more complex just because you're trying to do things that are much smaller. But if we do it intelligently and we have the right tools, we can keep designing without a problem.

Trihy: It probably says something that the two foundries that are represented here are going with FinFETs. But it's also the case that I read that Chenming Hu says the scalability of the ultrathin SOI is unproven as you go to 14nm and 10 nm nodes.

Another technology that is beginning to emerge...is 2.5 D where you can have multiple dies on a single interposer. That's another wildcard that we may see that emerge and get more interest for SOC design in the coming years.

Soenen: If you do an interposer, you sidestep the problem. If you don't put your analog on the same chip as your digital then you don't have a problem.

Brian Fuller

Related stories:

NVidia’s Bill Dally: Chip Design Should Take Days, Not Months

DAC 2013 -- Kaufman Winner Hu: FinFETs Will Serve Analog Design Very Well 

 

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