Answers to Top 10 Questions on Performing ECOs in EDI System
By Brian Wallace
on April 17, 2013
Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to physically implement ECOs efficiently and accurately...
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Filed under: ECO, LEC, synthesis, Encounter digital Implementation system, MMMC, tips and tricks, Cadence EDI System
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Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis
By Kari Summers
on March 26, 2013
When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use...
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Filed under: power analysis, EPS, EDI, flip chip, rail analysis, Five-Minute tutorial, bump
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CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
By Vasu Madabushi
on March 10, 2013
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user...
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Filed under: Digital Implementation, Encounter Digital Implementation, low power, EDI, SoC, Avago, CDNLive, digital, RC-Physical, CDNLive! Cadence, Cortex-A15, ARM, Cortex-A7, CCOpt, NVidia, ARMv8, GigaOpt, Cortex-A57, CDNLive Silicon Valley, high performance, AppliedMicro
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Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells
By Kari Summers
on February 22, 2013
In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current...
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Filed under: Digital Implementation, LEF, power analysis, low power, encounter power system, EPS, power, signoff, IR Drop, five minute tutorial, EM, rail analysis, current density, standard cells, power-grid views, QRC
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Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation (EDI) System
By Mukesh
on February 12, 2013
Everyone knows that the increasing speed and complexity of today's designs implies a significant increase in power consumption, which demands better optimization of your design for power. I am sure lot of us must be scratching our heads over how to...
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Filed under: Encounter Digital Implementation, EDI, EDI system, Encounter digital Implementation system, leakage, EDI 11, EDI 11.1, optLeakagePower, Leakage Optimization, Power Optimization, dynamic power, Jaiswal, 8 ways, low power tips, Vt partition
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Five-Minute Tutorial: Creating An EM Model File
By Kari Summers
on January 14, 2013
One of the least-fun parts of running power and rail analysis has always been coming up with the electromigration (EM) model file. In the past, this involved cracking open the process design rule manual, finding the appropriate equations, and creating...
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Filed under: power analysis, EPS, EDI, five minute tutorial, rail analysis, iRCX, ict, EM Model, electromigration
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SPICE Correlation Made Easy by Encounter Timing System (ETS)
By Mukesh
on December 10, 2012
Hello, and welcome to my first blog! As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE...
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Filed under: Encounter Timing System, STA, static timing analysis, Spectre, ETS, signoff, ETS create_spice_deck, spice correlation, mukesh, app note, spice
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The Case for the Tiny Testcase
By Robert Dwyer
on November 16, 2012
I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue they've observed on their design and I'm...
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Filed under: Digital Implementation, verification, encounter, testcase, test, test case, debug, tiny testcase, small testcase, Bob Dwyer
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Transitioning Your LEF-Based EDI System Design Flow to OpenAccess
By Brian Wallace
on November 12, 2012
The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage...
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Filed under: Digital Implementation, blog, Virtuoso, encounter, LEF, mixed signal, EDI system, mixed-signal, Cadence Online Support, Brian Wallace, OpenAccess, PDK, OA, LEF to OpenAccess
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Five-Minute Tutorial: Why You Should Be Running Early DRC
By Kari Summers
on October 11, 2012
Everyone knows you have to run signoff DRC before you tape out a design. Sometimes, DRC is left to exactly that moment - right before the tapeout. If major problems are found in the design at that point, the tapeout either has to be delayed, or there...
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Filed under: DRC, EDI, Encounter digital Implementation system, signoff, NanoRoute, Verify Geometry, metal fill, memories, routing access, macros, power grid, filler, IP, welltap, endcap, early DRC
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