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Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

Comments(0)Filed under: Digital Implementation, Digital Implementation forums, Encounter Digital Implementation, EDI, EDI system, Cadence Online Support, signoff, Encounterer Digital Implementation System, digital implementation, Tempus, timing signoff

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through http://support.cadence.com

Rapid Adoption Kits:

Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2

With the help of this RAK (rapid adoption kit) you will learn how to perform static timing analysis on a dual-tone multi-frequency (DTMF) design using Cadence Tempus Timing Signoff Solution in each of the four modes shown below:

Tempus STA      Single Mode Single Corner                 SMSC
Tempus STA      Distributed Multi-Mode Multi-Corner     DMMMC
Tempus STA      Concurrent Multi-Mode Multi-Corner     CMMMC
Tempus DSTA    Distributed STA on multiple clients      Tempus DSTA

You will be able to:

•    Understand how to set up and run each of the Tempus Timing Signoff Solution methods

•    Report and analyze static timing results

•    Be confident on how to start your new design and choose the methods that are best for you

Timing Signoff Optimization (TSO) using TEMPUS 13.2 & EDI System 13.2

In this RAK, you will learn how to perform ECOs (engineering change orders) for solving hold, setup, and DRV timing violations on a dual-tone multi-frequency (DTMF) design using Tempus Timing Signoff Solution and Cadence Encounter Digital Implementation System.
First section of this will cover Tempus TSO fixing on a block-level design and the subsequent will cover hierarchical chip finishing using Tempus TSO.

This will help to:

•    Explain how to investigate timing in an signoff STA environment
•    Understand and explain the timing ECO methodology
•    Understand and perform all the steps required before starting the ECO process
•    Perform hold, setup, and DRV timing fixes through ECOs
•    Report and analyze ECO results
•    Implement the ECOs in Encounter Digital Implementation System
•    Verify final signoff STA
•    Assemble a hierarchical design in Tempus Timing Signoff Solution for STA and ECO fixing
•    Perform hierarchically aware chip finishing with timing ECOs
•    Optimize timing in replicated modules (master/clone)

Videos :

Demo on Implementing Hierarchical Design Using EDI System

This knowledge resource is meant for beginners, new users of EDI System, or users new to the digital implementation design flow. This will help users to learn steps needed in specifying the partitions, creating power and ground rings, running placement and trial/route, assigning partition pins, deriving timing budgets, committing the partitions, pushing into the partitions, and, finally, saving the partitions.

How to create and use ILM (Interface Logic Model) in EDI system

This video showcases steps required in creating the ILMs of a partitioned block, implementation of created ILMs at the top level, and checking of interface logic at the top level of the specified ILM and viewing path, penetrating into the block up to interface logic of the path.

Hope you find these knowledge resources useful.

Happy Learning!
Mukesh Jaiswal


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