Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking trends in ARMv8 64-bit processor based microservers for power efficient cloud computing/data centers and high-end content generating superphones and tablets have thrown new curveballs at chip designers. As we're aware, battery technology hasn't kept pace with Moore's Law and as a result some amazing recent advances in process technology (such as FinFET, double patterning, etc.) and EDA tools are helping offset the difficulties in designing power efficient yet high-performance SoCs.
I'm really pleased to see a lineup of exciting papers in the High-Performance Digital Implementation track at the upcoming CDNLive Silicon Valley in Santa Clara, March 12, from some of the heavy hitters in the industry. These presentations describe the implementation of SoCs for a multitude of designs such as ARM Cortex-A core-based applications processors with state-of-the-art GPUs for demanding high-end smartphones and tablets; the world's first multi-Gigahertz ARMv8 64-bit processor architecture based server-on-chip for cloud computing/data centers; and complex networking ASICs, to name a few.
Rounding off the sessions are interesting papers from ARM on implementing their latest 64-bit Cortex-A57 processor based on the ARMv8 architecture and processor optimization pack (POP) IP development for ARM's big.LITTLETM paradigm -- with Cortex-A15 and Cortex-A7 processors respectively -- with Cadence's Encounter digital flows. These presentations exemplify the strong partnership and collaboration between ARM and Cadence in developing implementation reference methodologies (iRM) that ease designing ARM processors into leading-edge SoCs and accelerate time-to-market.
A common thread that the audience will hear is the significant power, performance and area (PPA) improvements customers have been able to achieve with some of the key Cadence tools such as RTL Compiler-Physical (RCP) and Encounter Digital Implementation (EDI) System featuring the latest GigaOpt physical optimization and Clock Concurrent Optimization (CCOpt) technologies. RCP, GigaOpt and CCOpt form the three pillars of Cadence's strong offering for implementing complex and high-performance designs in silicon. Some of the key advances include extending GigaOpt to the entire optimization flow (pre- and post-route) with full multi-CPU support, route-driven and layer-aware optimization at advanced nodes, and native integration of CCOpt in EDI, all leading to significant PPA improvements. Stop by the Cadence booth at the partner expo to learn more about the upcoming EDI release 13.1 highlights!
I've always been fascinated by our customers' end-products and verticals (going beyond just chip design and into adjacencies) where Cadence's tools have been used for bleeding-edge designs. So when companies such as AppliedMicro, ARM, Avago and NVidia come to town to graciously share their design experiences, one can't help but sit up and take notice! CDNLive gives a wonderful opportunity for attendees to understand the intricacies behind implementing these complex SoCs, including the challenges faced-from synthesis, design planning to final implementation, signoff and everything in between-and how they surmounted them. Key takeaways include lessons learned and best practices that the audience can readily deploy into their own designs and methodologies. That's the beauty of CDNLive-it provides ample opportunities to learn from fellow designers while extending one's professional network. What more can you ask for?
On Wednesday, March 13, the R&D luncheon offers a unique opportunity for our customers to sit down with our R&D and product engineers to discuss the chip-design problems of the day. We've set up thematic tables to cater to different areas of focus, including Advanced Node (28/20/16/14nm), Clock Concurrent Optimization, Implementing GHz+ ARM Cortex-A processor based designs, low-power, mixed-signal, signoff, and more! This offers an informal atmosphere for Cadence to also better understand our customers' requirements.
Here's a sneak peek into the paper presentations in the high-performance track on March 12, 2013:
- In Session HP105 (4:45-5:35pm), Sumbal Rafiq of AppliedMicro will present "X-Gene: Realizing a complex high-performance and power efficient 64-bit multicore ARMv8 based server-on-chip solution in silicon". This revolutionary multi-gigahertz design targets the extremely demanding cloud-computing/datacenter market. With multi-core ARMv8 CPUs, network interface controller (NIC), high-speed interconnect fabric, memory and other peripherals, the design complexity has reached unprecedented levels, throwing several new challenges in chip integration and meeting stringent PPA metrics. AppliedMicro and Cadence have collaborated from an early stage of development to deploy an RTL-to-GDSII flow based on Cadence's Encounter Digital tools to successfully implement and tape out the design. The proof's in working silicon!
- Session HP 104 (9:00-9:50am) titled "High Performance/Low Power Implementation of ARM Cortex-A15 and Cortex-A7 with ARM POP IP for ARM big.LITTLE Systems and Applications" will be presented by Sathyanath Subramanian from ARM. Sathya will talk about ARM's big.LITTLE heterogeneous processing concept and how the ARM POP IP optimized with Cadence's flows at advanced nodes provides designers a head start and a PPA boost for implementing designs with Cortex-A15 and Cortex-A7 processors.
- In Session HP103 (2:30-3:20pm), Brent McKanna of ARM will present Targeting High Frequency and Power Efficient Implementations for ARM's High Performance Cortex-A57 Processor. Cortex-A57 is ARM's latest and highest performing ARMv8 64-bit processor targeting the enterprise server and high-end smartphone/tablet applications, where maintaining high power efficiencies at superior performance points are critical. ARM and Cadence have collaborated throughout the development of Cortex-A57 to create an RTL-to-signoff flow based on Cadence Encounter design tools. The paper describes the techniques used for handling the increased complexity of larger ARM cores and for closing designs on advanced nodes such as 28nm.
- Session HP102 (1:30-2:20pm) titled Advanced Strategies for Timing Closure Utilizing New GigaOpt Features will be presented by Jack Benzel of Avago Technologies. Given the explosive growth in the number of large memory macros and the growing dominance of RC delays limiting long-haul wire performance at advanced nodes, new strategies are required to address low-latency architectures. Jack's paper will cover several of EDI System's new GigaOpt features including low-RC layer promotion, advanced re-buffering, TNS focus, path balancing, and path compaction. Get exposed to real-world 28nm examples demonstrating before/after QOR improvements.
- In Session HP101 (3:45-4:35pm), Santosh Navale of NVidia will present Implementing high performance GHz+ mobile applications processors and GPU with clock concurrent design techniques. Hear about how NVidia changed their clocking methodology to tackle several hundred complex generated and interacting clock signals, which form the back-bone of modern applications processors. Hear how they handled on-chip-variation, complex clock gating, multi-mode/multi-corner, and low-power requirements while improving chip performance with the Cadence clock concurrent optimization (CCOpt) technology on multi-Gigahertz ARM CPU based mobile applications and GeForce GPU processors.
Registration and program information for CDNLive Silicon Valley is available here.