Home > Community > Blogs > Digital Implementation > five minute tutorial why you should be running early drc
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Digital Implementation blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Five-Minute Tutorial: Why You Should Be Running Early DRC

Comments(0)Filed under: DRC, EDI, Encounter digital Implementation system, signoff, NanoRoute, Verify Geometry, metal fill, memories, routing access, macros, power grid, filler, IP, welltap, endcap, early DRC
Everyone knows you have to run signoff DRC before you tape out a design. Sometimes, DRC is left to exactly that moment - right before the tapeout. If major problems are found in the design at that point, the tapeout either has to be delayed, or there is a mad scramble to fix the issues. This is a situation no one wants to find themselves in.

Running DRC early and often is very much worth the effort. In addition to the general benefits of having the DRC deck and flow set up early so that it's pushbutton later in the project (there are often switches for metal stack, RDL type, bump pitch, etc that need to be selected), I recommend running DRC at the following milestones:

Power grid in place, no cell placement or signal routing. Hard macros/IP may be placed.
Running DRC here will make sure that your power grid is DRC clean. It can be very costly to have to fix power grid issues around signal routing late in the flow. Also, a majority of DRC issues can occur in power grid vias. Getting this clean early will put you ahead of the game. If your memories/IP/other macros are already placed, you'll be verifying the power connections to them as well, and you'll also make sure they are placed far enough apart from each other.

All cells placed (including macros/IP and filler cells), but no signal routing. 
Checking DRC at this point is critical. You need to make sure you have all required welltaps and/or endcaps, and that they are spaced appropriately. Having to fix this later in the flow will mean moving functional cells and affecting your timing. You also want to make sure that any IP or memory blocks have the appropriate spacing between each other and to standard cells. Alignment marker cells are required in many processes, so you'll want to check that you've got that right as well. Don't forget to add standard cell fillers before this run! If you leave out the fillers, you'll have a ton of DRC violations to wade through! You also want to make sure your fill methodology follows any VT spacing rules, and the no-filler1 rule if that exists for your process. (For more info on that particular issue, see Five-Minute Tutorial: Avoiding The Use Of FILL1 Cells.)

As soon as you have the first cut of the design with all cells placed and all signal routing complete.
This can be a big one too. If this is a new process, you may be vetting the LEF routing rules. In a tested process, the routing will usually be ok, but you may have routing access issues to memories or IP that may be using outdated blockage methods. I see a lot of this with memories where the blockage does not go to the edge of the block (the recommended method) so that NanoRoute can access the pins in a planar fashion. You may need to edit the macro blockages, and you'll want to do this at the beginning of the project when you're not in so much of a rush.

After the first pass of metal fill.
I often see DRC violations regarding metal fill spacing from the edge and corners of the design. If you're using a signoff fill utility, you probably don't need to worry about this. But most of the time, metal fill is done in Encounter Digital Implementation System (EDI) so that the timing effects can be seen easily. In that case, you may need to add some routing blockage or adjust your fill settings to get DRC-clean fill. It's also important to make sure you're hitting the metal density targets. A special note: be on the lookout for MAX density violations! It can and does happen, and it's harder to fix than min density.

If you've done all this, then you can continue intermediate DRC checks as you near tapeout and you shouldn't have that much to fix in the final days of your design.

EDI users will be familiar with the verifyGeometry command. I highly recommend running this before you start any of the DRC runs listed above! The verifyGeometry function is not a complete signoff check, but it will point out almost all of your metal DRC issues (and also shorts). Signoff DRC is still needed to check layers below M1 (since EDI uses LEF and not full layouts). But if you proceed to DRC without running verifyGeometry, you're not saving yourself any time. Fix what you can in EDI with verifyGeometry first; then you'll be in very good shape for early DRC!
You may also be interested in this post: Simple Steps To Debug DRC Violations Undetected In EDI System.

- Kari Summers


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.