Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings to achieve routing success?
Fortunately, the application note on NanoRoute Recommended Options is available to help answer these questions. Many of you are utilizing it already but I wanted to highlight it here because it has been recently updated. If you have not referenced this app note in the past, I highly recommend using it. The app note provides the recommended NanoRoute settings with a focus on 32nm and 28nm design nodes. But it is useful regardless of what process node you're designing at. It covers:
- Unnecessary NanoRoute options which are no longer needed for routing using NanoRoute
- Post Route double cut insertion
- Recommended routing strategies for double cut insertion
- Recommended NanoRoute scripts for increased double-cut vias insertion targeting TSMC 28nm
- Recommended NanoRoute scripts for increased double-cut vias insertion targeting IBM 32/28nm technologies
- NanoRoute debugging options
I personally reference multi-cut via insertion flows on pages 5 and 6 on a regular basis. These flows describe a good, better and best approach providing the options to run concurrent and/or post-route insertion of multi-cut vias.
But multi-cut via insertion only works if you have a proper set of multi-cut vias defined. If you're using one of the major foundries they often will provide a technology LEF file with an optimal set of vias for NanoRoute.
If you are developing your own technology LEF consider using the generateVias flow. This flow is described in Solution 11774588. The generateVias command, introduced in EDI 11, will analyze the VIARULE ... GENERATE DEFAULT rules and the cut layer rules (spacing, width, enclosure, etc.) in the LEF to create the optimal set of vias for NanoRoute. generateVias usage is supported for 40nm and below.
For example, you describe a template for how the vias should be generated:
VIARULE M7_M6 GENERATE DEFAULT
LAYER Metal6 ;
ENCLOSURE 0.005 0.03 ;
LAYER Via6 ;
RECT -0.035 -0.035 0.035 0.035 ;
SPACING 0.14 BY 0.14 ;
RESISTANCE 5.000000 ;
LAYER Metal7 ;
ENCLOSURE 0.005 0.03 ;
Then prior to NanoRoute run generateVias to optimal vias:
I hope this helps you achieve routing success!
- Brian Wallace