Home > Community > Blogs > Digital Implementation > five minute tutorial avoid si problems with better pin placement in edi
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Digital Implementation blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Five-Minute Tutorial: Avoid SI Problems With Better Pin Placement In Encounter Digital Implementation (EDI)

Comments(0)Filed under: Digital Implementation, encounter, SI analysis, noise analysis, EDI 10.1, five minute tutorial, assignPtnPin, pin placement

I know we're over halfway through January already (where does the time go?), but Happy New Year everyone! I hope 2012 is a good one for your business and your chip designs, and let's hope the Mayans just ran out of ink when they were finishing the calendar for this year.

Today I'd like to highlight an option of the assignPtnPin command that was added in Encounter Digital Implementation System (EDI) 10.1. This option is called -improveSI. Sounds intriguing and helpful, right? Let's see how it works:

If you use the command assignPtnPin -improveSI, then the pin assignment will attempt to place pins such that pins on the same layer are not on adjacent tracks. Also the pin assignment will attempt to place pins such that you don't have pins on top of each other in consecutive preferred-direction layers.

For example, if one pin is placed in M4, then the -improveSI option will attempt not to place another M4 pin on the closest track to either side of the first pin, and will also attempt not to place an M6 or M2 pin in the same spot as the original M4 pin.

I keep saying "attempt" because I'm guessing that legal placement will trump -improveSI, so if you have lots of pins on a small block, or have strict limits on pin layers, following the -improveSI rules may not always be possible.

I have not used this option myself yet, so give it a try and report back how you like it!

Here are some other tips to avoid SI problems:

Five-Minute Tutorial: Fixing SI Victim Nets

Five-Minute Tutorial: Setting Up Clock Routing Rules

- Kari Summers

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.