Now that Wei Lii Tan has helped you with your New Year’s
resolution to “create a chip that is so compelling …” in his previous
blog, I would like to help you understand how Cadence is using our signoff
qualified engines during the design implementation flow to reduce your time to
Anyone remember the story of the tortoise and the hare from
your childhood? The moral of the story is that simply being fast isn’t always
better, and in a way that is very much like using signoff quality engines
during the design implementation flow. Let me explain …
Traditional design methodologies that have been established
over the years were optimized for runtime, mostly by trading off accuracy. By
reducing runtimes at points in the design where accuracy wasn’t needed, a
design could progress more rapidly to signoff. On the surface, this seems like
a very logical approach to take. However, deeper analysis shows that this might
not always enable the fastest time to tapeout.
While the runtime for individual parts of the flow can be
improved by trading off accuracy for increased performance, many of Cadence’s
customers have already reflected that the bigger problem is repeating
implementation steps to address violations that are only found during late-stage
In fact, such customers have already experienced that using
signoff quality engines during the design implementation flow actually improves time to tapeout by enabling
better convergence in the solution. While it does take slightly longer to run
the signoff engines in the flow, the additional time is quite small compared to
having to repeat steps through the back-end design methodology to fix problems.
OK, let’s get even more specific with an example.
Consider that the routing engine of an ASIC solution does
not manage all of the additional complex rules required at 28nm and below.
After the routing is finally completed, often following many optimization loops
to address timing violations, the design meets the timing
requirements and is ready for final signoff. Unfortunately, signoff DRC
checking now flags that the router didn’t meet all of the design rules, forcing
the design team to fix the routing … but the router isn’t aware of the complex
rules that have failed, and so an automated fix is impossible. Instead, the
design team must manually fix the additional DRC violations, and that’s ECO
Now consider the alternative solution. The router is enabled
with signoff quality DRC checking and so avoids creating DRC violations …
admittedly, the router takes slightly longer to run, but once timing closure is
attained, the design team can have confidence that no additional DRC violations
will be found at signoff.
While the above example explains how time to tapeout can be
improved for DRC checking, consider that all signoff components could result in
similar issues. At Cadence, I am proud that we have a very comprehensive suite
of signoff solutions that can execute separate standalone signoff, or enable our
signoff engines integrated within our Virtuoso custom IC and Encounter digital
Included in the
signoff suite are products that enable the following functionality (Cadence
product names are in parentheses)
Parasitic extraction (Cadence QRC Extraction)
- Physical verification (Cadence PVS Design Rule Checker and Cadence PVS Layout vs Schematic Checker)
Static timing and SI analysis (Encounter Timing
Power integrity analysis (Encounter Power
Litho hotspot detection and analysis (Cadence
Litho Electrical Analyzer and Cadence Litho Physical Analyzer)
CMP analysis (Cadence CMP Predictor).
So, just like the tortoise and hare story, faster
runtimes might sound like the best option, but faster time to tapeout requires
a different approach.