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Evolution of Design Exploration and Planning

Comments(0)Filed under: Floorplanning and Prototyping, First Encounter, partitioning, Encounter Digital Implementation, Floorplanning, EDI, EDI system, Encounter digital Implementation system, Digital end-to-end flow

The great architect Frank Lloyd Wright once said "you can fix it on the drafting board with an eraser, or on the construction site with a sledge hammer." The semiconductor design industry is a perfect example where finding issues later in the flow can be extremely expensive. Chips that fail in high-volume consumer products can cost companies hundreds of millions or even a billion dollars, and there is huge benefit to validating the design and identifying and fixing issues early in the design process.

To address this issue, First Encounter introduced the concept of design exploration and planning in IC design nearly 10 years ago. This enabled designers to build early prototypes of their chips and resolve issues that usually came late in the design cycle, along the critical path toward reaching final tapeout. This significantly reduced the overall turn-around time of the design flow and provided huge gains in productivity and predictability of the design process and schedule. Design exploration and planning has since become an integral part of any IC design flow and has changed significantly over the years to keep up with the growing chip size and complexity in accordance with Moore's Law.  

Robust Hierarchical Methodology

While hierarchical methodologies were fairly immature back in the days as most designs were done flat or bottom-up, today any productive design exploration and planning solution requires a robust hierarchical methodology to support the big designs of today. Cadence has been a leader in this area, and both First Encounter and the Encounter Digital Implementation System support various hierarchical design styles such as channel-based, channel-less, micro-channels or master-clone.

The hierarchical support in Encounter helps physical designers assess how best to partition the logical hierarchy into physical modules by analyzing the optimal pin assignments; creating accurate time budgets; accurately predicting the clock distribution networks; analyzing the power grids; and eventually generating complete timing and physical constraints for each of the physical modules. To further handle the Giga-Gate designs of today, we have developed a new data abstraction technology. This unique capability allows netlist compression up to 90% while maintaining relevant timing and congestion information, resulting in faster turnaround time and one pass implementation handoff.

Implementation Quality Automation

In addition, the growing chip functionality in a shrinking time to market window demands increasing automation to get early feedback, while still providing results good enough for implementation. A case in point is the automation in macro placement. To address the ever-increasing number of hard macros on a design, Automated Floorplan Synthesis in First Encounter now enables concurrent standard cell and macro placement that helps designers to generate implementation quality floorplans for both flat and hierarchical designs.

The Floorplan Ranking capability further empowers designers to general multiple floorplans in parallel and rank them based on different criteria such as timing and area. This enables designers to do a quick feasibility analysis and make informed trade-offs early in the floorplanning stage.

Low-Power Support

Furthermore, there is growing concern for advanced-node support and low-power today as wireless chips dominate the consumer market. To address this, First Encounter also supports the Common Power Format (CPF), advanced low-power techniques, and design-for-yield capabilities that are critical for power hungry and advanced node designs.

First Encounter today is an integral part of the Cadence Digital End-to-End Solution. It paves the way for Silicon Realization by providing a comprehensive design planning and debug environment that captures the design intent upfront, enables large scale designs with its unique abstraction capabilities and provides a predictable convergent path for hierarchical design closure. With the ever-growing chip complexity, design planning and prototyping will continue to gain significance in the IC design flow. The pay-offs will be in the form of overall increased productivity, predictability and profitability. I am sure we will continue to see growing innovation in this area and it will be fascinating to see how this space reshapes in the future.

Abha Maheshwari




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