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3D-IC TSV Realization: The Race Has Begun!

Comments(0)Filed under: Digital Implementation, Floorplanning, 3DIC, 3D, TSV, thermal, test, packaging, 3D-IC

3D IC discussions are creating quite a buzz these days. No conference is complete without a mention of 3D ICs, and there are reasons behind that. 3D ICs using through-silicon vias (TSVs) help you meet challenging performance and power targets to serve the growing demands of the networking, graphics, wireless, and computing industries. And don't forget consumer needs for ultra light and thin devices! 

If you have anything to do with memories or with GPUs, or with designing logic to interact with the analog and RF components for the markets I mentioned above, you probably know what I am talking about. If you have not looked at 3D-IC TSV technology yet, it's a good time to do so now.

What's Needed for 3D IC Realization

There are a few technology requirements for 3D IC Silicon Realization:

  • An integrated digital, analog and packaging environment: This serves as a foundation to enable heterogonous integration of various components like analog, RF, logic, and memories, which may be at different process nodes, for 3D IC stacks. Any solution is incomplete if it can't marry these platforms together.
  • 3D floorplanning and implementation: This environment helps with critical tasks such as placing microbumps for TSVs, optimizing the stack for timing and thermal management, routing the signal and power lines across multiple die, and placing landing pads.
  • Thermal and IR drop analysis: Signal integrity, IR drop, and thermal analysis and management become very critical on stacked chips. One can only imagine how easy it will be to melt a chip if memory and logic are not stacked properly. Heating and cooling are important considerations.
  • Design for Test: During the 3D Panel at the recent LSI Innovation Acceleration conference, 3D design for test (DFT) was agreed upon as a challenge in this space. How will we test the entire system and diagnose potential problems? Who will own the stack and yield issues - foundries or OSATs?
  • System level exploration: This is certainly important once we start planning in 3D, but I think there are many other problems for 3D community to sort out before this.

I began studying this technology years ago wondering if it would ever become real. I remember when a colleague of mine shared an article that he had written 22 years ago that had a mention of 3D ICs. But now I can see that it is real because the need is real and is urgent. Moore's Law is not going anywhere anymore, "more" needs to be done to deal with the CMOS scaling trend, and 3D IC is that "more" right now.

We are seeing a lot of traction at some of our key customers who are now taping out real production chips. 3D IC technology has its share of open challenges, like any other disruptive technology in its early stages, but the performance and power benefits are so huge that it is certainly serving as a differentiating strategy for the few who have dared to walk that path.

So unarguably the race is on.

Are you in it yet? Let me know; let's talk about it. Please let us know if you would like to see the technology in action.

Samta Bansal

Recent Cadence Community blogs on 3D ICs:

Samta Bansal: My DATE With 3DIC Technology

Rahul Deokar: EDP Symposium Discovers an Inconvenient Truth with a Shot of 3D

Richard Goering: EDA Workshop: A Reality Check on 3D ICs

Rahul Deokar: DAC 2010 - A "Coming Out" Party for 3D-IC Design

Richard Goering: 3D-IC TSV Update: No Technology Roadblocks, But Cost Management is Needed

Recent Webinar on 3D IC Topics:

Should You Design Your Next System With 3D TSVs? Hear from GLOBALFOUNDRIES and Cadence

 

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